GLSVLSI 1998 TABLE OF CONTENTS

Acknowledgments
Organizing Committee
GLS-VLSI'98 Program Committee
Foreword
Message from the Steering Committee Chair

Low Power Circuits and Architectures

Low Power Memory Architectures for Video Applications [p. 2]

Bhanu Kapoor

Reducing Power Consumption of Dedicated Processors through Instruction Set Encoding [p. 8]

Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino

A Low-Power High-Performance Embedded SRAM Macrocell [p. 13]

A.M. Fahim, M. Khellah, and M.I. Elmasry

Low-Power Design of Finite Field Multipliers for Wireless Applications [p. 19]

A.G. Wassal, M.A. Hassan, and M.I. Elmasry

Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems [p. 26]

Dusan Suvakovic, C. Andre T. Salama

A Bootstrapped NMOS Charge Recovery Logic [p. 30]

Seung-Moon Yoo and Sung-Mo (Steve) Kang

Power Reducing Techniques for Clocked CMOS PLAs [p. 34]

R.F. Hobson

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines [p. 39]

Yehea I. Ismail, Eby G. Friedman, and Jose L. Neves

A New Full Adder Cell for Low-Power Applications [p. 45]

Ahmed M. Shams, and Magdy A. Bayoumi

VLSI Circuits

Beta-Driven Threshold Elements [p. 52]

Victor I. Varshavsky

A VLSI High-Performance Encoder with Priority Lookahead [p. 59]

José G. Delgado-Frias and Jabulani Nyathi

Noise Margins of Threshold Logic Gates Containing Resonant Tunneling Diodes [p. 65]

M. Bhattacharya and P. Mazumder

600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications [p. 71]

Azman M. Yusof, Lim Chu Aun & S.M. Rezaul Hasan

Stability of a Continuous-Time State Variable Filter with Op-amp and OTA-C Integrators [p. 77]

Tim Bakken, John Choma, Jr.

Multiple-Valued Logic Voltage-Mode Storage Circuits Based on True-Single-Phase Clocked Logic [p. 83]

I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, and T. Stouraitis

CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation [p. 89]

J. Navarro S. Jr. and Wilhelmus A. M. Van Noije

Design of Clock Distribution Networks in Presence of Process Variations [p. 95]

M. Nekili, Y. Savaria, and G. Bois

Design of an 8:1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology [p. 103]

J. Navarro S., Jr. and W.A.M. Van Noije

Issues in the Design of Domino Logic Circuits [p. 108]

Pranjal Srivastava, Andrew Pua, and Larry Welch

A Novel 1.5-V CMOS Mixer [p. 113]

G. Giustolisi, G. Palmisano, G. Palumbo, and C. Strano

Analysis of Adaptive CMOS Down Conversion Mixers [p. 118]

C.K. Sandalci and S. Kiaei Can K. Sandalci

Artificial Neural Network Electronic Nose for Volatile Organic Compounds [p. 122]

Hoda S. Abdel-Aty-Zohdy

VLSI Architectures

A VLSI Self-Compacting Buffer for DAMQ Communication Switches [p. 128]

José G. Delgado-Frias and Richard Diaz

A Dictionary Machine Emulation on a VLSI Computing Tree System [p. 134]

A.E. Harvin III and J.G. Delgado-Frias

Modeling and Analysis of the Difference-Bit Cache [p. 140]

Ashutosh Kulkarni, Navin Chander, Soumya Pillai and Lizy John

Modeling of Shift Register-Based ATM Switch [p. 146]

Sandeep Agarwal and Fayez El-Guibaly

An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement [p. 152]

Jen-Chien Tuan, Chein-Wei Jen

MPEG-2 Video Decoder for DVD [p. 157]

Nien-Tsu Wang, Chen-Wei Shih, Duan Juat Wong-Ho, Nam Ling

A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine [p. 161]

Eric SENN, Bertrand ZAVIDOVIQUE

Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning [p. 168]

BA. Alhalabi, Q. Malluhi, and R. Ayoubi Bassem A. Alhalabi, Qutaibah Malluhi, Rafic Ayoubi

VLSI Arithmetic

Residue to Binary Number Converters for (2ⁿ - 1,2ⁿ,2ⁿ + 1) [p. 174]

Yuke Wang, Xiaoyu Song, Mostapha Aboulhamid

The Design of Residue Number System Arithmetic Units for a VLSI Adaptive Equalizer [p. 179]

Inseop Lee and W. Kenneth Jenkins

An Efficient Residue to Weighted Converter for a New Residue Number System [p. 185]

Alexander Skavantzos

The Chinese Abacus Method: Can We Use It for Digital Arithmetic? [p. 192]

Franco Maloberri, Clien Gang

Merged Arithmetic for Computing Wavelet Transforms [p. 196]

Gwangwoo Choe and Earl E. Swartzlander, Jr.

Digital Arithmetic Using Analog Arrays [p. 202]

S. Sadeghi-Emamchaie, G.A Jullien, V. Dimitrov, and W. C. Miller

A Combined Interval and Floating Point Multiplier [p. 208]

James E. Stine and Michael J. Schulte

Testing

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling [p. 216]

Irith Pomeranz and Sudhakar M. Reddy

Random Self-Test Method Applications on PowerPC^TM Microprocessor Caches [p. 222]

Rajesh Raina,Robert Molyneaux

A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection [p. 230]

B. Provost, A.M. Brosa, and E. Sánchez-Sinencio

VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection [p. 237]

F.S. Bietti, F. Ferrandi, F. Fummi, and D. Sciuto

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits [p. 243]

Hendrawan Soeleman, Dinesh Somasekhar, and Kaushik Roy

A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits [p. 249]

K. Raahemifar and M. Ahmadi

VLSI Communication Circuits and Systems

Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications [p. 258]

Robert H. Caverly

Design Issues of LC Tuned Oscillators for Integrated Transceivers [p. 264]

C. Samori, A.L. Lacaita, A. Zanchi, and P. Vita

Novel Simple Models of CML Propagation Delay [p. 270]

M. Alioto and G. Palumbo

Next Generation Narrowband RF Front-Ends in Silicon IC Technology [p. 275]

John R. Long

Low Voltage Low Power CMOS AGC Circuit for Wireless Communication [p. 281]

Hassan 0. Elwan, Mohammed Ismail

A Continuous-Time Switched-Current ΣΔ Modulator with Reduced Loop Delay [p. 286]

Louis Luh, John Choma,Jr., Jeffrey Draper

Design Methodologies and CAD Tools Algorithms

An Exact Input Encoding Algorithm for BDDs Representing FSMs [p. 294]

Wilsin Gosti, Tiziano Villa, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli

Maximum Current Estimation in Programmable Logic Arrays [p. 301]

S. Bobba and I.N.Hajj

Mutually Disjoint Signals and Probability Calculation in Digital Circuits [p. 307]

Vishwani D. Agrawal, Sharad Seth

Identifying High-Level Components in Combinational Circuits [p. 313]

Travis Doom, Jennifer White, Anthony Wojcik, Greg Chisholm

Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints [p. 319]

Anthony D. Johnson

Linear Transformations and Exact Minimization of BDDs [p. 325]

Wolfgang Günther, Roif Drechsler

Timed Supersetting and the Synthesis of Large Telescopic Units [p. 331]

L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino

Tabu Search Based Circuit Optimization [p. 338]

Sadiq M. Sait, Habib Youssef, and Munir M. Zahra

On the Characterization of Multi-Point Nets in Electronic Designs [p. 344]

Dirk Stroobandt, Fadi I. Kurdahi

Formal Verification

HOOVER: Hardware Object-Oriented Verification [p. 351]

Mostafa M. Aref, and Khaled M. Elleithy

MDG-Based Verification by Retiming and Combinational Transformations [p. 356]

O.A. Mohamed, E. Cerny, and X. Song

Practical Considerations in Formal Equivalence Checking of PowerPC^TM Microprocessors [p. 362]

A. Chandra, L.-C. Wang, and M. Abadir

Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS [p. 368]

J. Lu and S. Tahar

Design Methods

Performance Optimization of Self-Timed Circuits [p. 374]

M.A. Franklin and P. Prabhu

Stochastic Evolution Algorithm for Technology Mapping [p. 380]

A.S. Al-Mulhem, A. Amin, and H. Youssef

RCRS: A Framework for Loop Scheduling with Limited Number of Registers [p. 386]

Kaisheng Wang, Ted Zhihong Yu, Edwin H. -M. Sha

A Quantitative Study of the Benefits of Area-I/O in FPGAs [p. 392]

Herwig Van Marck, Jo Depreitere, Dirk Stroobandt and Jan Van Campenhout

Top-Down Design Using Cycle Based Simulation: An MPEG A/V Decoder Example [p. 400]

Dale E. Hocevar, Ching-Yu Hung, Dan Pickens and Sundararajan Sriram

Low Power

Low-Power Driven Scheduling and Binding [p. 406]

Jim Crenshaw and Majid Sarrafzadeh

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation [p. 414]

Muhammad M. Khellah and M. I. Elmasry

A Methodology for High Level Power Estimation and Exploration [p. 420]

V. Krishna and N. Ranganathan

How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs [p. 426]

S. Gailhard, N. Julien, J. -Ph. Diguet, and E. Martin

Database for CAD

Sharing Electronic Design Data Via Semantic Spaces [p. 432]

K.C. Davis, S. Venkatesan, and L.M.L. Delcambre

VHDL-Based EDA Tool Implementation with Java [p. 440]

R. Miller

Standard Data Representations for VLSI Algorithm Development [p. 446]

D. Hertweck, M. Nica, S. Park, and C. Purdy

A Storage Structure for Graph-Oriented Databases Using an Array of Element Types [p. 452]

T. Hochin and T. Tsuji