The 12th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Wednesday, January 24, 2007

A	B	C	D
1K (Small Auditorium, 5F) Opening Session and Keynote Address I 8:30 - 10:00
1A (Room 411+412) DFM in Physical Design 10:15 - 12:20	1B (Room 413) SoC Software Design and Performance Analysis 10:15 - 12:20	1C (Room 414+415) Advances in High-Frequency and High-Speed Circuit Design and CAD 10:15 - 12:20	1D (Room 416+417) University Design Contest 10:15 - 12:20
2A (Room 411+412) New Techniques in Placement 13:30 - 15:35	2B (Room 413) On Chip Communication Methodology 13:30 - 15:35	2C (Room 414+415) Analog CAD Techniques: From Analysis to Verification 13:30 - 15:35	2D (Room 416+417) SPECIAL SESSION: Design for Manufacturability 13:30 - 15:35
3A (Room 411+412) Routing 16:00 - 18:05	3B (Room 413) System Synthesis and Optimization Techniques 16:00 - 18:05	3C (Room 414+415) Model Checking and Applications to Digital and Analog Circuits 16:00 - 18:05	3D (Room 416+417) SPECIAL SESSION: Embedded Software for Multiprocessor Systems-on-Chip 16:00 - 18:05

Thursday, January 25, 2007

A	B	C	D
2K (Small Auditorium, 5F) Keynote Address II 9:00 - 10:00
4A (Room 411+412) Model Order Reduction and Macromodeling 10:15 - 12:20	4B (Room 413) System Level Modeling 10:15 - 12:20	4C (Room 414+415) Logic Synthesis 10:15 - 12:20	4D (Room 416+417) SPECIAL SESSION: EDA Challenges for Analog/RF 10:15 - 12:20
5A (Room 411+412) Statistical Interconnect Modeling and Analysis 13:30 - 15:35	5B (Room 413) Optimization Issues in Embedded Systems 13:30 - 15:35	5C (Room 414+415) High-Level Synthesis 13:30 - 15:35	5D (Small Auditorium, 5F) Designers' Forum Panel : Presilicon SoC HW/SW Verification 13:30 - 15:35
6A (Room 411+412) Timing Modeling and Optimization 16:00 - 18:05	6B (Room 413) Application Examples with Leading Edge Design Methodology 16:00 - 18:05	6C (Room 414+415) Module/Circuit Synthesis 16:00 - 18:05	6D (Small Auditorium, 5F) Designers' Forum: Low-power SoC Technologies 16:00 - 17:50

Friday, January 26, 2007

A	B	C	D
3K (Small Auditorium, 5F) Keynote Address III 9:00 - 10:00
7A (Room 411+412) Advanced Methods for Leakage Reduction 10:15 - 12:20	7B (Room 413) Uncertainty Aware Interconnect Design 10:15 - 12:20	7C (Room 414+415) Test Cost Reduction Techniques 10:15 - 12:20	7D (Room 416+417) SPECIAL SESSION: Multi-Processor Platforms for Next Generation Embedded Systems 10:15 - 12:20
8A (Room 411+412) Advancement in Power Analysis and Optimization 13:30 - 15:35	8B (Room 413) Electrical Optimization in Floorplanning/Placement 13:30 - 15:35	8C (Room 414+415) Advances in Test and Diagnosis 13:30 - 15:35	8D (Small Auditorium, 5F) Designers' Forum: High-speed Chip to Chip Signaling Solutions 13:30 - 15:35
9A (Room 411+412) Power Efficient Design Techniques 16:00 - 18:05	9B (Room 413) Leading Edge Design Methodology for Processors 16:00 - 18:05	9C (Room 414+415) Satisfiability and Applications 16:00 - 18:05	9D (Small Auditorium, 5F) Designers' Forum Panel: Top 10 Design Issues 16:00 - 18:05

List of Papers

Remark: The presenter of each paper is marked with "*".

Wednesday, January 24, 2007

Session 1K Opening Session and Keynote Address I
Time: 8:30 - 10:00 Wednesday, January 24, 2007
Location: Small Auditorium, 5F
Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

1K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-chains
Author	Rob A. Rutenbar (Carnegie Mellon Univ., United States)
Detailed information (abstract, keywords, etc)

Session 1A DFM in Physical Design
Time: 10:15 - 12:20 Wednesday, January 24, 2007
Location: Room 411+412
Chairs: Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Toshiyuki Shibuya (Fujitsu Lab., Japan)

1A-1 (Time: 10:15 - 10:40)

Title	Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process
Author	*Subarna Sinha, Jianfeng Luo, Charles Chiang (Synopsys, United States)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)
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1A-2 (Time: 10:40 - 11:05)

Title	Fast and Accurate OPC for Standard-Cell Layouts
Author	*David M. Pawlowski, Liang Deng, Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)
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1A-3 (Time: 11:05 - 11:30)

Title	Coupling-aware Dummy Metal Insertion for Lithography
Author	*Liang Deng (Univ. of Illinois, Urbana-Champaign, United States), Kaiyuan Chao (Intel Co., United States), Hua Xiang (IBM, United States), Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)
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1A-4 (Time: 11:30 - 11:55)

Title	Fast Buffer Insertion for Yield Optimization under Process Variations
Author	Ruiming Chen, *Hai Zhou (Northwestern Univ., United States)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)
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1A-5 (Time: 11:55 - 12:20)

Title	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Author	*Bao Liu, Andrew Kahng, Xu Xu (Univ. of California, San Diego, United States), Jiang Hu, Ganesh Venkataraman (Texas A&M Univ., United States)
Page	pp. 25 - 31
Detailed information (abstract, keywords, etc)
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Session 1B SoC Software Design and Performance Analysis
Time: 10:15 - 12:20 Wednesday, January 24, 2007
Location: Room 413
Chairs: Qiang Zhu (Fujitsu Lab., Japan), Youn-Long Steve Lin (National Tsing-Hua Univ., Taiwan)

1B-1 (Time: 10:15 - 10:40)

Title	Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
Author	Axel Siebenborn, *Alexander Viehl, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany)
Page	pp. 32 - 37
Detailed information (abstract, keywords, etc)
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1B-2 (Time: 10:40 - 11:05)

Title	Software Performance Estimation in MPSoC Design
Author	Marcio Oyamada, *Flavio Wagner (UFRGS, Brazil), Marius Bonaciu (TIMA Lab., France), Wander Cesario (MnD, France), Ahmed Jerraya (TIMA Lab., France)
Page	pp. 38 - 43
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1B-3 (Time: 11:05 - 11:30)

Title	Effective OpenMP Implementation and Translation for Multiprocessor System-On-Chip without using OS
Author	*Woo-Chul Jeun, Soonhoi Ha (Seoul National Univ., Republic of Korea)
Page	pp. 44 - 49
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1B-4 (Time: 11:30 - 11:55)

Title	Creating Explicit Communication in SoC Models Using Interactive Re-Coding
Author	*Pramod Chandraiah, Junyu Peng, Rainer Doemer (Univ. of California, Irvine, United States)
Page	pp. 50 - 55
Detailed information (abstract, keywords, etc)
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1B-5 (Time: 11:55 - 12:20)

Title	System Architecture for Software Peripherals
Author	*Siddharth Choudhuri, Tony Givargis (Univ. of California, Irvine, United States)
Page	pp. 56 - 61
Detailed information (abstract, keywords, etc)
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Session 1C Advances in High-Frequency and High-Speed Circuit Design and CAD
Time: 10:15 - 12:20 Wednesday, January 24, 2007
Location: Room 414+415
Chairs: Jaijeet Roychowdhury (Univ. of Minnesota, United States), Tomohisa Kimura (Toshiba, Japan)

1C-1 (Time: 10:15 - 10:40)

Title	A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates
Author	Xiren Wang, *Wenjian Yu, Zeyi Wang (Tsinghua Univ., China)
Page	pp. 62 - 67
Detailed information (abstract, keywords, etc)
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1C-2 (Time: 10:40 - 11:05)

Title	Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers
Author	Arthur Nieuwoudt, Tamer Ragheb, *Yehia Massoud (Rice Univ., United States)
Page	pp. 68 - 73
Detailed information (abstract, keywords, etc)
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1C-3 (Time: 11:05 - 11:30)

Title	PLLSim - An Ultra Fast Bang-bang Phase Locked Loop Simulation Tool
Author	*Michael James Chan, Adam Postula (Univ. of Queensland, Australia), Yong Ding (NanoSilicon Pty Ltd, Australia)
Page	pp. 74 - 79
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1C-4 (Time: 11:30 - 11:55)

Title	A Programmable Fully-Integrated GPS receiver in 0.18µm CMOS with Test Circuits
Author	Mahta Jenabi, *Noshin Riahi, Ali Fotowat-Ahmadi (Unistar Micro Technology Inc., Canada)
Page	pp. 80 - 85
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1C-5 (Time: 11:55 - 12:20)

Title	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
Author	Swarup Bhunia, *Massood Tabib Azar, Daniel Saab (Case Western Reserve Univ., United States)
Page	pp. 86 - 91
Detailed information (abstract, keywords, etc)
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Session 1D University Design Contest
Time: 10:15 - 12:20 Wednesday, January 24, 2007
Location: Room 416+417
Chairs: Makoto Nagata (Kobe Univ., Japan), Fumio Arakawa (Hitachi, Japan)

1D-1 (Time: 10:15 - 10:20)

Title	A 1Tb/s 3W Inductive-Coupling Transceiver Chip
Author	*Noriyuki Miura, Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 92 - 93
Detailed information (abstract, keywords, etc)
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1D-2 (Time: 10:20 - 10:25)

Title	22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors
Author	*Ahmet Oncu, B.B.M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima (Univ. of Tokyo, Japan)
Page	pp. 94 - 95
Detailed information (abstract, keywords, etc)
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1D-3 (Time: 10:25 - 10:30)

Title	A 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18µm CMOS
Author	*Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi (Gunma Univ., Japan), Masao Hotta (Musashi Inst. of Tech., Japan)
Page	pp. 96 - 97
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1D-4 (Time: 10:30 - 10:35)

Title	A Wideband CMOS LC-VCO Using Variable Inductor
Author	*Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 98 - 99
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1D-5 (Time: 10:35 - 10:40)

Title	Design of Active Substrate Noise Canceller using Power Suplly di/dt Detector
Author	*Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Page	pp. 100 - 101
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1D-6 (Time: 10:40 - 10:45)

Title	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
Author	*Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu (Inst. of Communications Engineering, NTHU, Taiwan), Shuo-Hung Hsu (Inst. of Electronics Engineering, NTHU, Taiwan)
Page	pp. 102 - 103
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1D-7 (Time: 10:45 - 10:50)

Title	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation
Author	*Satoshi Fukuda, Daisuke Kawazoe, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 104 - 105
Detailed information (abstract, keywords, etc)
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1D-8 (Time: 10:50 - 10:55)

Title	Pseudo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems
Author	*Chee Hong Ivan Lai, Minoru Fujishima (Univ. of Tokyo, Japan)
Page	pp. 106 - 107
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1D-9 (Time: 10:55 - 11:00)

Title	Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique
Author	Roel Pantonial, Md. Ashfaquzzaman Khan, *Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ., Japan)
Page	pp. 108 - 109
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1D-10 (Time: 11:00 - 11:05)

Title	Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
Author	*Li-Chun Lin, Shih-Hao Ou (National Chiao Tung Univ., Taiwan), Tay-Jyi Lin (Industrial Technology Research Institute, Taiwan), Siang-Sen Deng, Chih-Wei Liu (National Chiao Tung Univ., Taiwan)
Page	pp. 110 - 111
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1D-11 (Time: 11:05 - 11:10)

Title	A Highly Integrated 8 mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16 MHz SoC Platform
Author	Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, *Wei-Cheng Hung, Kai-Yuan Jan (National Tsing Hua Univ., Taiwan)
Page	pp. 112 - 113
Detailed information (abstract, keywords, etc)
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1D-12 (Time: 11:10 - 11:15)

Title	Configurable AMBA On-Chip Real-Time Signal Tracer
Author	*Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 114 - 115
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1D-13 (Time: 11:15 - 11:20)

Title	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
Author	*Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ., Japan), Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu (ROHM, Japan)
Page	pp. 116 - 117
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1D-14 (Time: 11:20 - 11:25)

Title	A Multi-Drop Transmission-Line Interconnect in Si LSI
Author	*Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 118 - 119
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1D-15 (Time: 11:25 - 11:30)

Title	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology
Author	*Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 120 - 121
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1D-16 (Time: 11:30 - 11:35)

Title	A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations
Author	*Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 122 - 123
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1D-17 (Time: 11:35 - 11:40)

Title	A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
Author	*Minoru Watanabe, Fuminori Kobayashi (Kyushu Inst. of Tech., Japan)
Page	pp. 124 - 125
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1D-18 (Time: 11:40 - 11:45)

Title	Low-Power High-Speed 180-nm CMOS Clock Drivers
Author	*Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi (Chuo Univ., Japan)
Page	pp. 126 - 127
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Session 2A New Techniques in Placement
Time: 13:30 - 15:35 Wednesday, January 24, 2007
Location: Room 411+412
Chairs: Shin'ichi Wakabayashi (Hiroshima City Univ., Japan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)

2A-1 (Time: 13:30 - 13:55)

Title	Fast Analytic Placement using Minimum Cost Flow
Author	*Ameya R Agnihotri, Patrick H Madden (SUNY Binghamton, United States)
Page	pp. 128 - 134
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2A-2 (Time: 13:55 - 14:20)

Title	FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
Author	*Natarajan Viswanathan, Min Pan, Chris Chu (Iowa State Univ., United States)
Page	pp. 135 - 140
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2A-3 (Time: 14:20 - 14:45)

Title	Hippocrates: First-Do-No-Harm Detailed Placement
Author	Haoxing Ren (IBM, United States), *David Pan (Univ. of Texas, Austin, United States), Charles J Alpert, Gi-Joon Nam, Paul Villarrubia (IBM, United States)
Page	pp. 141 - 146
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2A-4 (Time: 14:45 - 15:10)

Title	ECO-system: Embracing the Change in Placement
Author	*Jarrod Roy, Igor Markov (Univ. of Michigan, United States)
Page	pp. 147 - 152
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2A-5 (Time: 15:10 - 15:35)

Title	Bisection Based Placement for the X Architecture
Author	*Satoshi Ono (SUNY Binghamton CSD, United States), Sameer Tilak (Supercomputer Center, United States), Patrick H. Madden (SUNY Binghamton CSD, United States)
Page	pp. 153 - 158
Detailed information (abstract, keywords, etc)
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Session 2B On Chip Communication Methodology
Time: 13:30 - 15:35 Wednesday, January 24, 2007
Location: Room 413
Chairs: Soonhoi Ha (Seoul National Univ., Republic of Korea), Nikil Dutt (Univ. of California, Irvine, United States)

2B-1 (Time: 13:30 - 13:55)

Title	Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems
Author	*Minje Jun, Kwanhu Bang (Yonsei Univ., Republic of Korea), Hyuk-Jun Lee (Cisco Systems Incorporated, United States), Naehyuck Chang (Seoul National Univ., Republic of Korea), Eui-Young Chung (Yonsei Univ., Republic of Korea)
Page	pp. 159 - 164
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2B-2 (Time: 13:55 - 14:20)

Title	A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses
Author	*Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 165 - 170
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2B-3 (Time: 14:20 - 14:45)

Title	Communication Architecture Synthesis of Cascaded Bus Matrix
Author	*Junhee Yoo, Dongwook Lee (Seoul National Univ., Republic of Korea), Sungjoo Yoo (Samsung Electronics, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 171 - 177
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2B-4 (Time: 14:45 - 15:10)

Title	Topology Exploration for Energy Efficient Intra-tile Communication
Author	*Jin Guo, Antonis Papanikolaou, Francky Catthoor (IMEC, Belgium)
Page	pp. 178 - 183
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2B-5 (Time: 15:10 - 15:35)

Title	Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
Author	Krishnan Srinivasan, *Karam S. Chatha, Goran Konjevod (Arizona State Univ., United States)
Page	pp. 184 - 190
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Session 2C Analog CAD Techniques: From Analysis to Verification
Time: 13:30 - 15:35 Wednesday, January 24, 2007
Location: Room 414+415
Chair: Yasuaki Inoue (Waseda Univ., Japan)

2C-1 (Time: 13:30 - 13:55)

Title	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
Author	*Jiayi Liu, Sheqin Dong, Yunchun Ma, Di Long, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 191 - 196
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2C-2 (Time: 13:55 - 14:20)

Title	A Graph Reduction Approach to Symbolic Circuit Analysis
Author	*Guoyong Shi, Weiwei Chen (Shanghai Jiao Tong Univ., China), C.-J. Richard Shi (Univ. of Washington, United States)
Page	pp. 197 - 202
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2C-3 (Time: 14:20 - 14:45)

Title	Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic
Author	Xuexin Liu, *Wai-Shing Luk, Yu Song, Xuan Zeng (Fudan Univ., China)
Page	pp. 203 - 208
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2C-4 (Time: 14:45 - 15:10)

Title	WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design
Author	*Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng (Fudan Univ., China)
Page	pp. 209 - 214
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2C-5 (Time: 15:10 - 15:35)

Title	Structured Placement with Topological Regularity Evaluation
Author	*Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Page	pp. 215 - 220
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Session 2D SPECIAL SESSION: Design for Manufacturability
Time: 13:30 - 15:35 Wednesday, January 24, 2007
Location: Room 416+417
Chair: Keh-Jeng Chang (National Tsing Hua Univ., Taiwan)

2D-1 (Time: 13:30 - 13:50)

Title	(Invited Paper) Modeling Sub-90nm On-chip Variation Using Monte Carlo Method for DFM
Author	Jun-Fu Huang, *Victor Chang, Sally Liu, Kelvin Doong (TSMC, Taiwan), Keh-Jeng Chang (National Tsing-Hua Univ., Taiwan)
Page	pp. 221 - 225
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2D-2 (Time: 13:50 - 14:10)

Title	(Invited Paper) DFM Reality in Sub-nanometer IC Design
Author	Nishath Verghese, *Philippe Hurat (Clear Shape Technologies, United States)
Page	pp. 226 - 231
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2D-3 (Time: 14:10 - 14:30)

Title	(Invited Paper) DFM/DFY Practices During Physical Designs for Timing, Signal Integrity, and Power
Author	Shi-Hao Chen, *Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai (Global Unichip, Taiwan)
Page	pp. 232 - 237
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2D-4 (Time: 14:30 - 14:50)

Title	(Invited Paper) Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
Author	Chung-Wei Lin (National Taiwan Univ., Taiwan), Ming-Chao Tsai, Kuang-Yao Lee (National Tsing Hua Univ., Taiwan), Tai-Chen Chen (National Taiwan Univ., Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 238 - 243
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2D-5 (Time: 14:50 - 15:35)

Title	(Panel Discussion) Design for Manufacturability
Author	Organizer: Keh-Jeng Chang, Moderator: Keh-Jeng Chang (National Tsing-Hua Univ., Taiwan), Panelists: Kelvin Doong (TSMC, Taiwan), Nishath Verghese (Clear Shape, United States), Ke-Cheng Chu (Global Unichip, Taiwan), Ting-Chi Wang (National Tsing-Hua Univ., Taiwan), Andrew Kahng (Univ. of California, San Diego and Blaze DFM, United States)
Detailed information (abstract, keywords, etc)

Session 3A Routing
Time: 16:00 - 18:05 Wednesday, January 24, 2007
Location: Room 411+412
Chairs: Martin Wong (Univ. of Illinois, Urbana-Champaign, United States), Youichi Shiraishi (Gunma Univ., Japan)

3A-1 (Time: 16:00 - 16:25)

Title	A Novel Performance-Driven Topology Design Algorithm
Author	*Min Pan, Chris Chu (Iowa State Univ., United States), Priyadarsan Patra (Intel Co., United States)
Page	pp. 244 - 249
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3A-2 (Time: 16:25 - 16:50)

Title	FastRoute 2.0: A High-quality and Efficient Global Router
Author	*Min Pan, Chris Chu (Iowa State Univ., United States)
Page	pp. 250 - 255
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3A-3 (Time: 16:50 - 17:15)

Title	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
Author	*Zhen Cao, Tong Jing (Tsinghua Univ., China), Jinjun Xiong, Yu Hu, Lei He (Univ. of California, Los Angeles, United States), Xianlong Hong (Tsinghua Univ., China)
Page	pp. 256 - 261
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3A-4 (Time: 17:15 - 17:40)

Title	A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction
Author	*Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 262 - 267
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3A-5 (Time: 17:40 - 18:05)

Title	A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks
Author	*Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata (Univ. of Kitakyushu, Japan)
Page	pp. 268 - 273
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Session 3B System Synthesis and Optimization Techniques
Time: 16:00 - 18:05 Wednesday, January 24, 2007
Location: Room 413
Chairs: Ren-Song Tsay (National Tsing Hua Univ., Taiwan), Ahmed Jerraya (TIMA, France)

3B-1 (Time: 16:00 - 16:25)

Title	LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Author	*Aseem Gupta, Nikil Dutt, Fadi Kurdahi (Univ. of California, Irvine, United States), Kamal Khouri, Magdy Abadir (Freescale Semiconductor Inc., United States)
Page	pp. 274 - 279
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3B-2 (Time: 16:25 - 16:50)

Title	Protocol Transducer Synthesis using Divide and Conquer Approach
Author	*Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 280 - 285
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3B-3 (Time: 16:50 - 17:15)

Title	A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units
Author	*Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Page	pp. 286 - 291
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3B-4 (Time: 17:15 - 17:40)

Title	Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture
Author	*Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan)
Page	pp. 292 - 297
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3B-5 (Time: 17:40 - 18:05)

Title	Architectural Optimizations for Text to Speech Synthesis in Embedded Systems
Author	*Soumyajit Dey, Monu Kedia, Anupam Basu (Indian Inst. of Tech. Kharagpur, India)
Page	pp. 298 - 303
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Session 3C Model Checking and Applications to Digital and Analog Circuits
Time: 16:00 - 18:05 Wednesday, January 24, 2007
Location: Room 414+415
Chairs: Igor Markov (Univ. of Michigan, United States), Shin'ichi Minato (Hokkaido Univ., Japan)

3C-1 (Time: 16:00 - 16:25)

Title	Deeper Bound in BMC by Combining Constant Propagation and Abstraction
Author	Roy Armoni (-, Israel), Limor Fix (Intel, United States), Ranan Fraer (Intel, Israel), *Tamir Heyman (Carnegie Mellon Univ., United States), Moshe Vardi (Rich Univ., United States), Yakir Vizel, Yael Zbar (Intel, Israel)
Page	pp. 304 - 309
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3C-2 (Time: 16:25 - 16:50)

Title	Efficient BMC for Multi-Clock Systems with Clocked Specifications
Author	*Malay K Ganai, Aarti Gupta (NEC, United States)
Page	pp. 310 - 315
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3C-3 (Time: 16:50 - 17:15)

Title	Symbolic Model Checking of Analog/Mixed-Signal Circuits
Author	*David Walter, Scott Little, Nicholas Seegmiller, Chris Myers (Univ. of Utah, United States), Tomohiro Yoneda (National Institute of Informatics, Japan)
Page	pp. 316 - 323
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3C-4 (Time: 17:15 - 17:40)

Title	Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
Author	*Marc Boule, Zeljko Zilic (McGill Univ., Canada)
Page	pp. 324 - 329
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Session 3D SPECIAL SESSION: Embedded Software for Multiprocessor Systems-on-Chip
Time: 16:00 - 18:05 Wednesday, January 24, 2007
Location: Room 416+417
Chairs: Hiroyuki Tomiyama (Nagoya Univ., Japan), Tei-Wei Kuo (National Taiwan Univ., Taiwan)

3D-1 (Time: 16:00 - 16:30)

Title	(Invited Paper) Model-based Programming Environment of Embedded Software for MPSoC
Author	*Soonhoi Ha (Seoul National Univ., Republic of Korea)
Page	pp. 330 - 335
Detailed information (abstract, keywords, etc)
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3D-2 (Time: 16:30 - 17:00)

Title	(Invited Paper) RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
Author	*Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Page	pp. 336 - 341
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3D-3 (Time: 17:00 - 17:30)

Title	(Invited Paper) Energy-efficient Real-time Task Scheduling in Multiprocessor DVS Systems
Author	*Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sheng Shih (National Taiwan Univ., Taiwan)
Page	pp. 342 - 349
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3D-4 (Time: 17:30 - 18:00)

Title	(Invited Paper) Towards Scalable and Secure Execution Platform for Embedded Systems
Author	*Junji Sakai, Hiroaki Inoue, Masato Edahiro (NEC, Japan)
Page	pp. 350 - 354
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Thursday, January 25, 2007

Session 2K Keynote Address II
Time: 9:00 - 10:00 Thursday, January 25, 2007
Location: Small Auditorium, 5F
Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

2K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Meeting with the Forthcoming IC Design - The Era of Power, Variability and NRE Explosion and a Bit of the Future -
Author	Takayasu Sakurai (The Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

Session 4A Model Order Reduction and Macromodeling
Time: 10:15 - 12:20 Thursday, January 25, 2007
Location: Room 411+412
Chairs: Sheldon Tan (Univ. of California, Riverside, United States), Yehia Massoud (Rice Univ., United States)

4A-1 (Time: 10:15 - 10:40)

Title	Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form
Author	Boyuan Yan, *Sheldon X.-D. Tan, Pu Liu (Univ. of California, Riverside, United States), Bruce McGaughy (Cadence Design Systems Inc., United States)
Page	pp. 355 - 360
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4A-2 (Time: 10:40 - 11:05)

Title	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods
Author	Sandeep Dabas, Ning Dong, *Jaijeet Roychowdhury (Univ. of Minnesota, Twin Cities, United States)
Page	pp. 361 - 366
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4A-3 (Time: 11:05 - 11:30)

Title	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos
Author	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China), Sheldon X.D-Tan (Univ. of California, Riverside, United States), *Le Kang (Tsinghua Univ., China)
Page	pp. 367 - 372
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4A-4 (Time: 11:30 - 11:55)

Title	Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation
Author	*Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud (Rice Univ., United States)
Page	pp. 373 - 378
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4A-5 (Time: 11:55 - 12:20)

Title	Frequency Selective Model Order Reduction via Spectral Zero Projection
Author	Mehboob Alam, *Arthur Nieuwoudt, Yehia Massoud (Rice Univ., United States)
Page	pp. 379 - 383
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Session 4B System Level Modeling
Time: 10:15 - 12:20 Thursday, January 25, 2007
Location: Room 413
Chairs: Tei-Wei Kuo (National Taiwan Univ., Taiwan), Shinya Honda (Nagoya Univ., Japan)

4B-1 (Time: 10:15 - 10:40)

Title	Abstract, Multifaceted Modeling of Embedded Processors for System Level Design
Author	*Gunar Schirner, Andreas Gerstlauer, Rainer Doemer (Univ. of California, Irvine, United States)
Page	pp. 384 - 389
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4B-2 (Time: 10:40 - 11:05)

Title	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC
Author	*Patrice Gerin, Hao Shen, Alexandre Chureau, Aimen Bouchhima, Ahmed Amine Jerraya (TIMA Laboratory, France)
Page	pp. 390 - 395
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4B-3 (Time: 11:05 - 11:30)

Title	A Retargetable Software Timing Analyzer Using Architecture Description Language
Author	*Xianfeng Li (Peking Univ., China), Abhik Roychoudhury, Tulika Mitra (National Univeristy of Singapore, Singapore), Prabhat Mishra (Univ. of Florida, United States), Xu Cheng (Peking Univ., China)
Page	pp. 396 - 401
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Session 4C Logic Synthesis
Time: 10:15 - 12:20 Thursday, January 25, 2007
Location: Room 414+415
Chairs: Deming Chen (Univ. of Illinois, Urbana-Champaign, United States), Yutaka Tamiya (Fujitsu Lab., Japan)

4C-1 (Time: 10:15 - 10:40)

Title	Automating Logic Rectification by Approximate SPFDs
Author	*Yu-Shen Yang (Univ. of Toronto, Canada), Subarna Sinha (Synopsys, United States), Andreas Veneris (Univ. of Toronto, Canada), Robert Brayton (Univ. of California, United States)
Page	pp. 402 - 407
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4C-2 (Time: 10:40 - 11:05)

Title	BddCut: Towards Scalable Symbolic Cut Enumeration
Author	*Andrew Chaang Ling, Jianwen Zhu (Univ. of Toronto, Canada), Stephen Dean Brown (Altera Toronto Technology Centre, Canada)
Page	pp. 408 - 413
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4C-3 (Time: 11:05 - 11:30)

Title	Node Mergers in the Presence of Don't Cares
Author	*Stephen Plaza, Kai-hui Chang, Igor Markov, Valeria Bertacco (Univ. of Michigan, United States)
Page	pp. 414 - 419
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4C-4 (Time: 11:30 - 11:55)

Title	Synthesis of Reversible Sequential Elements
Author	Min-Lung Chuang, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 420 - 425
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4C-5 (Time: 11:55 - 12:20)

Title	Recognition of Fanout-free Functions
Author	Tsung-Lin Lee, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 426 - 431
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Session 4D SPECIAL SESSION: EDA Challenges for Analog/RF
Time: 10:15 - 12:20 Thursday, January 25, 2007
Location: Room 416+417
Chair: Georges Gielen (Katholieke Universiteit Leuven, Belgium)

4D-1 (Time: 10:15 - 10:40)

Title	(Invited Paper) Design Tool Solutions for Mixed-signal/RF Circuit Design in CMOS Nanometer Technologies
Author	*Georges Gielen (Katholieke Universiteit Leuven, Belgium)
Page	pp. 432 - 437
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4D-2 (Time: 10:40 - 11:05)

Title	(Invited Paper) Challenges to Accuracy for the Design of Deep-submicron RF-CMOS Circuits
Author	*Sadayuki Yoshitomi (Toshiba Co., Japan)
Page	pp. 438 - 441
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4D-3 (Time: 11:05 - 11:30)

Title	(Invited Paper) Advanced Tools for Simulation and Design of Oscillators/PLLs
Author	Xiaolue Lai, *Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Page	pp. 442 - 449
Detailed information (abstract, keywords, etc)
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Session 5A Statistical Interconnect Modeling and Analysis
Time: 13:30 - 15:35 Thursday, January 25, 2007
Location: Room 411+412
Chairs: Hideki Asai (Shizuoka Univ., Japan), Weiping Shi (Texas A&M Univ., United States)

5A-1 (Time: 13:30 - 13:55)

Title	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
Author	Ying Zhou (Texas A&M Univ., United States), Zhuo Li (Pextra Corp., United States), Yuxin Tian, *Weiping Shi (Texas A&M Univ., United States), Frank Liu (IBM, United States)
Page	pp. 450 - 455
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5A-2 (Time: 13:55 - 14:20)

Title	Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion
Author	*Youngmin Kim (Univ. of Michigan of Ann Arbor, United States), Dusan Petranovic (Mentor Graphics, United States), Dennis Sylvester (Univ. of Michigan of Ann Arbor, United States)
Page	pp. 456 - 461
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5A-3 (Time: 14:20 - 14:45)

Title	New Block-based Statistical Timing Analysis Approaches without Moment Matching
Author	Ruiming Chen, *Hai Zhou (Northwestern Univ., United States)
Page	pp. 462 - 467
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5A-4 (Time: 14:45 - 15:10)

Title	Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
Author	Alexandar Mitev, Michael Marefact, Dongsheng Ma, *Janet Wang (Univ. of Arizona, Tucson, United States)
Page	pp. 468 - 473
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5A-5 (Time: 15:10 - 15:35)

Title	Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations
Author	*Jun Tao, Xuan Zeng (Fudan Univ., China), Wei Cai (Univ. of North Carolina, Charlotte, United States), Yangfeng Su (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, United States), Charles Chiang (Synopsys Inc., United States)
Page	pp. 474 - 479
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Session 5B Optimization Issues in Embedded Systems
Time: 13:30 - 15:35 Thursday, January 25, 2007
Location: Room 413
Chairs: Pai Chou (Univ. of California, Irvine, United States), Maziar Goudarzi (Kyushu Univ., Japan)

5B-1 (Time: 13:30 - 13:55)

Title	Retiming for Synchronous Data Flow Graphs
Author	Nikolaos Liveris, Chuan Lin, Jia Wang, *Hai Zhou (Northwestern Univ., United States), Prithviraj Banerjee (Univ. of Illinois, Chicago, United States)
Page	pp. 480 - 485
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5B-2 (Time: 13:55 - 14:20)

Title	Signal-to-Memory Mapping Analysis for Multimedia Signal Processing
Author	Ilie I. Luican, Hongwei Zhu, *Florin Balasa (Univ. of Illinois, Chicago, United States)
Page	pp. 486 - 491
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5B-3 (Time: 14:20 - 14:45)

Title	MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
Author	*Rajesh Kumar T. S. (Texas Instruments India, India), Ravikumar C. P. (Texas Instruments, India), Govindarajan R. (Indian Institute of Science, India)
Page	pp. 492 - 497
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5B-4 (Time: 14:45 - 15:10)

Title	A Run-Time Memory Protection Methodology
Author	*Udaya Seshua (Philips Semiconductors, India), Nagaraju Bussa (Philips Research, India), Bart Vermeulen (Philips Research, Netherlands)
Page	pp. 498 - 503
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5B-5 (Time: 15:10 - 15:35)

Title	Short-Circuit Compiler Transformation: Optimizing Conditional Blocks
Author	*Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau (Univ. of California, Irvine, United States)
Page	pp. 504 - 510
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Session 5C High-Level Synthesis
Time: 13:30 - 15:35 Thursday, January 25, 2007
Location: Room 414+415
Chairs: Ki-seok Chung (Hanyang Univ., Republic of Korea), Katsuharu Suzuki (NEC, Japan)

5C-1 (Time: 13:30 - 13:55)

Title	Optimization of Arithmetic Datapaths with Finite Word-Length Operands
Author	*Sivaram Gopalakrishnan, Priyank Kalla (Univ. of Utah, United States), Florian Enescu (Georgia State Univ., United States)
Page	pp. 511 - 516
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5C-2 (Time: 13:55 - 14:20)

Title	Exploiting Power-Area Tradeoffs in Behavioural Synthesis through Clock and Operations Throughput Selection
Author	*Marco A. Ochoa-Montiel, Bashir M. Al-Hashimi (Univ. of Southampton, Great Britain), Peter Kollig (Philips Semiconductors, Great Britain)
Page	pp. 517 - 522
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5C-3 (Time: 14:20 - 14:45)

Title	A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
Author	*Yazhuo Dong, Yong Dou (National Univ. of Defense Technology, China)
Page	pp. 523 - 528
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5C-4 (Time: 14:45 - 15:10)

Title	High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
Author	*Deming Chen (Univ. of Illinois, Urbana-Champaign, United States), Jason Cong, Yiping Fan, Zhiru Zhang (Univ. of California, Los Angeles, United States)
Page	pp. 529 - 534
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5C-5 (Time: 15:10 - 15:35)

Title	Numerical Function Generators Using Edge-Valued Binary Decision Diagrams
Author	*Shinobu Nagayama (Hiroshima City Univ., Japan), Tsutomu Sasao (Kyushu Inst. of Tech., Japan), Jon Butler (Naval Postgraduate School, United States)
Page	pp. 535 - 540
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Session 5D Designers' Forum Panel : Presilicon SoC HW/SW Verification
Time: 13:30 - 15:35 Thursday, January 25, 2007
Location: Small Auditorium, 5F

5D-1

Title	(Panel Discussion) Presilicon SoC HW/SW Verification
Author	Organizer: Tetsuji Sumioka, Moderator: Tetsuji Sumioka (SONY, Japan), Panelists: Jason Andrews (Cadence, United States), Graham Hellestrand (VaST Systems Technology, United States), Hidefumi Kurokawa (NEC Electronics, Japan), Ilya Klebanov (Advanced Micro Devices, Canada), Seiji Koino (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

Session 6A Timing Modeling and Optimization
Time: 16:00 - 18:05 Thursday, January 25, 2007
Location: Room 411+412
Chairs: Masanori Hashimoto (Osaka Univ., Japan), Charlie Chung-Ping Chen (National Taiwan Univ., Taiwan)

6A-1 (Time: 16:00 - 16:25)

Title	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Author	Chuan Lin (Magma Design Automation Inc., United States), *Hai Zhou (Northwestern Univ., United States)
Page	pp. 541 - 546
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6A-2 (Time: 16:25 - 16:50)

Title	An Efficient Computation of Statistically Critical Sequential Paths Under Retiming
Author	Mongkol Ekpanyapong (Intel Co., United States), Xin Zhao, *Sung Kyu Lim (Georgia Inst. of Tech., United States)
Page	pp. 547 - 552
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6A-3 (Time: 16:50 - 17:15)

Title	Fast Electrical Correction Using Resizing and Buffering
Author	Shrirang Karandikar, *Charles J Alpert, Mehmet Yildiz, Paul Villarrubia, Steve Quay, Tuhin Mahmud (IBM, United States)
Page	pp. 553 - 558
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6A-4 (Time: 17:15 - 17:40)

Title	SmartSmooth: A Linear Time Convexity Preserving Smoothing Algorithm for Numerically Convex Data with Application to VLSI Design
Author	Sanghamitra Roy (Univ. of Wisconsin-Madison, United States), *Charlie Chung-Ping Chen (National Taiwan Univ., Taiwan)
Page	pp. 559 - 564
Detailed information (abstract, keywords, etc)
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6A-5 (Time: 17:40 - 18:05)

Title	Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
Author	*Zhangcai Huang, Hong Yu (Waseda Univ., Japan), Atsushi Kurokawa (Sanyo Semiconductor Company, Japan), Yasuaki Inoue (Waseda Univ., Japan)
Page	pp. 565 - 570
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Session 6B Application Examples with Leading Edge Design Methodology
Time: 16:00 - 18:05 Thursday, January 25, 2007
Location: Room 413
Chairs: Ing-Jer Huang (National Sun-Yat-Sen Univ., Taiwan), Takeshi Ikenaga (Waseda Univ., Japan)

6B-1 (Time: 16:00 - 16:25)

Title	Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
Author	Hwisung Jung (Univ. of Southern California, United States), Andy Hwang (Broadcom Corp., United States), *Massoud Pedram (Univ. of Southern California, United States)
Page	pp. 571 - 576
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6B-2 (Time: 16:25 - 16:50)

Title	Approximation Algorithm for Process Mapping on Network Processor Architectures
Author	*Chris Ostler, Karam S. Chatha, Goran Konjevod (Arizona State Univ., United States)
Page	pp. 577 - 582
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6B-3 (Time: 16:50 - 17:15)

Title	Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture (RICA)
Author	*Zahid Khan, Tughrul Arslan (Univ. of Edinburgh, Great Britain)
Page	pp. 583 - 588
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6B-4 (Time: 17:15 - 17:40)

Title	VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Author	*Imran Ahmed, Tughrul Arslan (Univ. of Edinburgh, Great Britain)
Page	pp. 589 - 594
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6B-5 (Time: 17:40 - 18:05)

Title	A High-Throughput Low-Power AES Cipher for Network Applications
Author	Shin-Yi Lin, *Chih-Tsun Huang (National Tsing Hua Univ., Taiwan)
Page	pp. 595 - 600
Detailed information (abstract, keywords, etc)
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Session 6C Module/Circuit Synthesis
Time: 16:00 - 18:05 Thursday, January 25, 2007
Location: Room 414+415
Chairs: Shinji Kimura (Waseda Univ., Japan), TingTing Hwang (National Tsing Hua Univ., Taiwan)

6C-1 (Time: 16:00 - 16:25)

Title	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands
Author	*Ajay K. Verma, Paolo Ienne (Ecole Polytechnique Federale de Lausanne, Switzerland)
Page	pp. 601 - 608
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6C-2 (Time: 16:25 - 16:50)

Title	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Author	Jianhua Liu, Yi Zhu, Haikun Zhu (Univ. of California, San Diego, United States), John Lillis (Univ. of Illinois, Chicago, United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Page	pp. 609 - 615
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6C-3 (Time: 16:50 - 17:15)

Title	An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization
Author	Haikun Zhu, Yi Zhu, *Chung-Kuan Cheng (Univ. of California, San Diego, United States), David M. Harris (Harvey Mudd Colledge, United States)
Page	pp. 616 - 621
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6C-4 (Time: 17:15 - 17:40)

Title	Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation
Author	*Cheoljoo Jeong, Steven M. Nowick (Columbia Univ., United States)
Page	pp. 622 - 627
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6C-5 (Time: 17:40 - 18:05)

Title	Safe Delay Optimization for Physical Synthesis
Author	*Kai-hui Chang, Igor L. Markov, Valeria Bertacco (Univ. of Michigan at Ann Arbor, United States)
Page	pp. 628 - 633
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Session 6D Designers' Forum: Low-power SoC Technologies
Time: 16:00 - 17:50 Thursday, January 25, 2007
Location: Small Auditorium, 5F
Chairs: Haruyuki Tago (Toshiba Co., Japan), Kazutoshi Kobayashi (Kyoto Univ., Japan)

6D-1 (Time: 16:00 - 16:20)

Title	(Invited Paper) Plenary Talk --Overview on Low Power SoC Design Technology--
Author	*Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)
Page	pp. 634 - 636
Detailed information (abstract, keywords, etc)
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6D-2 (Time: 16:20 - 16:50)

Title	(Invited Paper) Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware
Author	*Masaru Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto (Renesas, Japan)
Page	pp. 637 - 643
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6D-3 (Time: 16:50 - 17:20)

Title	(Invited Paper) Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)
Author	*Koichi Mori, Masakazu Suzuki, Yasuo Ohara, Satoru Matsuo, Atsushi Asano (Toshiba, Japan)
Page	pp. 644 - 648
Detailed information (abstract, keywords, etc)
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6D-4 (Time: 17:20 - 17:50)

Title	(Invited Paper) Low Power Techniques for Mobile Application SoCs based on Integrated Platform "UniPhier"
Author	*Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita (Matsushita Electric Industrial, Japan)
Page	pp. 649 - 653
Detailed information (abstract, keywords, etc)
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Friday, January 26, 2007

Session 3K Keynote Address III
Time: 9:00 - 10:00 Friday, January 26, 2007
Location: Small Auditorium, 5F
Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

3K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) How Foundry can Help Improve your Bottom-line? Accuracy Matters!
Author	Fu-Chieh Hsu (Taiwan Semiconductor Manufacturing Company, Taiwan)
Detailed information (abstract, keywords, etc)

Session 7A Advanced Methods for Leakage Reduction
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 411+412
Chairs: Masanori Hashimoto (Osaka Univ., Japan), Ankur Gupta (Cadence Design System, United States)

7A-1 (Time: 10:15 - 10:40)

Title	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Author	Youngsoo Shin, Sewan Heo, *Hyung-Ock Kim (KAIST, Republic of Korea), Jung Yun Choi (Samsung Electronics, Republic of Korea)
Page	pp. 654 - 659
Detailed information (abstract, keywords, etc)
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7A-2 (Time: 10:40 - 11:05)

Title	Runtime Leakage Power Estimation Technique for Combinational Circuits
Author	*Yu-Shiang Lin, Dennis Sylvester (Univ. of Michigan, United States)
Page	pp. 660 - 665
Detailed information (abstract, keywords, etc)
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7A-3 (Time: 11:05 - 11:30)

Title	Logic and Layout Aware Voltage Island Generation for Low Power Design
Author	*Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 666 - 671
Detailed information (abstract, keywords, etc)
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7A-4 (Time: 11:30 - 11:55)

Title	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
Author	Tsung-Yi Wu, Jr-Luen Tzeng, *Kuang-Yao Chen (National Changhua Univ. of Education, Taiwan)
Page	pp. 672 - 677
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7A-5 (Time: 11:55 - 12:20)

Title	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs
Author	*Hassan Hassan, Mohab Anis, Mohamed Elmasry (Univ. of Waterloo, Canada)
Page	pp. 678 - 683
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Session 7B Uncertainty Aware Interconnect Design
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 413
Chairs: Chih-Tsun Huang (National Tsing Hua Univ., Taiwan), Takashi Sato (Tokyo Inst. of Tech., Japan)

7B-1 (Time: 10:15 - 10:40)

Title	Approaching Speed-of-light Distortionless Communication for On-chip Interconnect
Author	Haikun Zhu, Rui Shi (Univ. of California, San Diego, United States), Hongyu Chen (Synopsys Inc., United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Page	pp. 684 - 689
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7B-2 (Time: 10:40 - 11:05)

Title	Delay Uncertainty Reduction by Interconnect and Gate Splitting
Author	Vineet Agarwal, Jin Sun, Alexandar Mitev, *Janet Wang (Univ. of Arizona, Tucson, United States)
Page	pp. 690 - 695
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7B-3 (Time: 11:05 - 11:30)

Title	Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects
Author	*Charbel Akl, Magdy Bayoumi (Univ. of Louisiana, Lafayette, United States)
Page	pp. 696 - 701
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7B-4 (Time: 11:30 - 11:55)

Title	Fast Buffered Delay Estimation Considering Process Variations
Author	Tien-Ting Fang, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 702 - 707
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7B-5 (Time: 11:55 - 12:20)

Title	Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Author	*Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud (Rice Univ., United States)
Page	pp. 708 - 713
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Session 7C Test Cost Reduction Techniques
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 414+415
Chairs: Sudhakar M. Reddy (Univ. of Iowa, United States), Tomoo Inoue (Hiroshima City Univ., Japan)

7C-1 (Time: 10:15 - 10:40)

Title	Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Author	*Danella Zhao, Unni Chandran (Univ. of Louisiana, Lafayette, United States), Hideo Fujiwara (NAIST, Japan)
Page	pp. 714 - 719
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7C-2 (Time: 10:40 - 11:05)

Title	Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Author	*Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST, Japan), Alex Orailoglu (Univ. of California, San Diego, United States), Hideo Fujiwara (NAIST, Japan)
Page	pp. 720 - 725
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7C-3 (Time: 11:05 - 11:30)

Title	An Architecture for Combined Test Data Compression and Abort-on-Fail Test
Author	*Erik Larsson, Jon Persson (Linköpings Universitet, Sweden)
Page	pp. 726 - 731
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7C-4 (Time: 11:30 - 11:55)

Title	RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
Author	*Hao Fang, Chenguang Tong, Xu Cheng (Peking Univ., China)
Page	pp. 732 - 737
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7C-5 (Time: 11:55 - 12:20)

Title	Systematic Scan Reconfiguration
Author	*Ahmad Al-Yamani (KFUPM, Saudi Arabia), Narendra Devta-Prasanna (Univ. of Iowa, United States), Arun Gunda (LSI Logic, United States)
Page	pp. 738 - 743
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Session 7D SPECIAL SESSION: Multi-Processor Platforms for Next Generation Embedded Systems
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 416+417
Chair: Nikil Dutt (Univ. of California, Irvine, United States)

7D-1 (Time: 10:15 - 10:35)

Title	(Invited Paper) Configurable Multi-Processor Platforms for Next Generation Embedded Systems
Author	*David Goodwin, Chris Rowen, Grant Martin (Tensilica, United States)
Page	pp. 744 - 746
Detailed information (abstract, keywords, etc)
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7D-2 (Time: 10:35 - 10:55)

Title	(Invited Paper) ARM MPCore The Streamlined and Scalable ARM11 Processor Core
Author	*Kazuyuki Hirata (ARM, Japan), John Goodacre (ARM, Great Britain)
Page	pp. 747 - 748
Detailed information (abstract, keywords, etc)
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7D-3 (Time: 10:55 - 11:15)

Title	(Invited Paper) The Potential of Cell BE as a Platform Technology for Embedded Systems
Author	Peter Hofstee (IBM, United States)
Detailed information (abstract, keywords, etc)

7D-4 (Time: 11:15 - 11:35)

Title	(Invited Paper) Many-Core Platforms in Search for Supporting Tools
Author	Rudy Lauwereins (IMEC, Belgium)
Detailed information (abstract, keywords, etc)

7D-5 (Time: 11:35 - 11:55)

Title	(Invited Paper) Nomadik®: A Mobile Multimedia Application Processor Platform
Author	*Maurizio Paganini (STMicroelectronics, France)
Page	pp. 749 - 750
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7D-6 (Time: 11:55 - 12:20)

Title	(Panel Discussion) Multi-Processor Platforms for Next Generation Embedded Systems
Author	Organizer: Nikil Dutt, Moderator: Nikil Dutt (Univ. of California, Irvine, United States), Panelists: David Goodwin (Tensilica, United States), Kazuyuki Hirata (ARM, Japan), Peter Hofstee (IBM, United States), Rudy Lauwereins (IMEC, Belgium), Maurizio Paganini (STMicroelecronics, France)
Detailed information (abstract, keywords, etc)

Session 8A Advancement in Power Analysis and Optimization
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Room 411+412
Chairs: Youngsoo Shin (KAIST, Republic of Korea), Takayuki Watanabe (Univ. of Shizuoka, Japan)

8A-1 (Time: 13:30 - 13:55)

Title	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach
Author	*Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong (Tsinghua Univ., China), Sheldon X.-D. Tan (Univ. of California, Riverside, United States)
Page	pp. 751 - 756
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8A-2 (Time: 13:55 - 14:20)

Title	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Author	*Sanjay Pant, David Blaauw (Univ. of Michigan, United States)
Page	pp. 757 - 762
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8A-3 (Time: 14:20 - 14:45)

Title	Fast Placement Optimization of Power Supply Pads
Author	Yu Zhong, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 763 - 767
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8A-4 (Time: 14:45 - 15:10)

Title	Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid
Author	Yu Zhong, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 768 - 773
Detailed information (abstract, keywords, etc)
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8A-5 (Time: 15:10 - 15:35)

Title	A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
Author	Hanif Fatemi, Shahin Nazarian, *Massoud Pedram (Univ. of Southern California, United States)
Page	pp. 774 - 779
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Session 8B Electrical Optimization in Floorplanning/Placement
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Room 413
Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), David Pan (Univ. of Texas, Austin, United States)

8B-1 (Time: 13:30 - 13:55)

Title	Thermal-Aware 3D IC Placement Via Transformation
Author	Jason Cong, *Guojie Luo, Jie Wei, Yan Zhang (Univ. of California, Los Angeles, United States)
Page	pp. 780 - 785
Detailed information (abstract, keywords, etc)
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8B-2 (Time: 13:55 - 14:20)

Title	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
Author	Fayez Mohamood, Michael Healy, Sung Kyu Lim, *Hsien-Hsin S. Lee (Georgia Tech, United States)
Page	pp. 786 - 791
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8B-3 (Time: 14:20 - 14:45)

Title	On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Author	*Chao-Hung Lu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Page	pp. 792 - 797
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8B-4 (Time: 14:45 - 15:10)

Title	Voltage Island Generation under Performance Requirement for SoC Designs
Author	*Wai-Kei Mak, Jr-Wei Chen (National Tsing Hua Univ., Taiwan)
Page	pp. 798 - 803
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8B-5 (Time: 15:10 - 15:35)

Title	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Author	*Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 804 - 809
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Session 8C Advances in Test and Diagnosis
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Room 414+415
Chairs: Erik Larsson (Royal Inst. of Tech., Sweden), Xiaoging Wen (Kyushu Inst. of Tech., Japan)

8C-1 (Time: 13:30 - 13:55)

Title	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Author	*Seongmoon Wang, Wenlong Wei (NEC, United States)
Page	pp. 810 - 816
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8C-2 (Time: 13:55 - 14:20)

Title	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
Author	Zhuo Zhang, *Sudhakar Reddy (Univ. of Iowa, United States), Irith Pomeranz (Purdue Univ., United States)
Page	pp. 817 - 822
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8C-3 (Time: 14:20 - 14:45)

Title	A Wafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs
Author	Sudarshan Bahukudumbi, Sule Ozev, *Krishnendu Chakrabarty (Duke Univ., United States), Vikram Iyengar (IBM, United States)
Page	pp. 823 - 828
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8C-4 (Time: 14:45 - 15:10)

Title	Fault Dictionary Size Reduction for Million-Gate Large Circuits
Author	*Yu-Ru Hong, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Page	pp. 829 - 834
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8C-5 (Time: 15:10 - 15:35)

Title	Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
Author	*Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li (National Taiwan Univ., Taiwan)
Page	pp. 835 - 840
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Session 8D Designers' Forum: High-speed Chip to Chip Signaling Solutions
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Small Auditorium, 5F
Chairs: Haruyuki Tago (Toshiba Co., Japan), Kazutoshi Kobayashi (Kyoto Univ., Japan)

8D-1 (Time: 13:30 - 14:00)

Title	(Invited Paper) Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation
Author	*Atsushi Hiraishi, Toshio Sugano (Elpida Memory, Japan), Hideki Kusamitsu (Yamaichi Electronics, Japan)
Page	pp. 841 - 845
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8D-2 (Time: 14:00 - 14:30)

Title	(Invited Paper) Xbox360_TM Front Side Bus - A 21.6 Gb/s End to End Interface Design
Author	*David Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane (IBM, United States), Jeff Johnson (Cadence Design Systems, United States)
Page	pp. 846 - 853
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8D-3 (Time: 14:30 - 15:00)

Title	(Invited Paper) Design Consideration of 6.25 Gbps Signaling for High-Performance Server
Author	*Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone (Fujitsu Laboratories of America, United States)
Page	pp. 854 - 857
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8D-4 (Time: 15:00 - 15:30)

Title	(Invited Paper) System Co-Design and Co-Analysis Approach to Implementing the XDR^TM Memory System of the Cell Broadband Engine^TM Processor Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production
Author	*Wai-Yeung Yip, Scott Best, Wendemagegnehu Beyene, Ralf Schmitt (Rambus, United States)
Page	pp. 858 - 865
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Session 9A Power Efficient Design Techniques
Time: 16:00 - 18:05 Friday, January 26, 2007
Location: Room 411+412
Chairs: Hiroyuki Tomiyama (Nagoya Univ., Japan), Gang Zeng (Nagoya Univ., Japan)

9A-1 (Time: 16:00 - 16:25)

Title	Flow Time Minimization under Energy Constraints
Author	*Jian-Jia Chen (National Taiwan Univ., Taiwan), Kazuo Iwama (Kyoto Univ., Japan), Tei-Wei Kuo, Hseuh-I Lu (National Taiwan Univ., Taiwan)
Page	pp. 866 - 871
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9A-2 (Time: 16:25 - 16:50)

Title	Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
Author	Bita Gorjiara, Nader Bagherzadeh, *Pai Chou (Univ. of California, Irvine, United States)
Page	pp. 872 - 877
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9A-3 (Time: 16:50 - 17:15)

Title	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
Author	*Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ., Japan)
Page	pp. 878 - 883
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9A-4 (Time: 17:15 - 17:40)

Title	Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
Author	*Subhasis Banerjee (Sun Microsystems, India), Surendra G, S. K. Nandy (Indian Institute of Science, India)
Page	pp. 884 - 889
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9A-5 (Time: 17:40 - 18:05)

Title	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
Author	*Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 890 - 895
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Session 9B Leading Edge Design Methodology for Processors
Time: 16:00 - 18:05 Friday, January 26, 2007
Location: Room 413
Chairs: Takashi Miyamori (Toshiba, Japan), Hideharu Amano (Keio Univ., Japan)

9B-1 (Time: 16:00 - 16:25)

Title	Design Methodology for 2.4GHz Dual-Core Microprocessor
Author	Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, *Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda (Fujitsu Ltd., Japan)
Page	pp. 896 - 901
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9B-2 (Time: 16:25 - 16:50)

Title	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools
Author	*Fu-Ching Yang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Page	pp. 902 - 907
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9B-3 (Time: 16:50 - 17:15)

Title	A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
Author	*Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan (Univ. of Edinburgh, Great Britain)
Page	pp. 908 - 913
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9B-4 (Time: 17:15 - 17:40)

Title	Exploration of Low Power Adders for a SIMD Data Path
Author	*Giacomo Paci (Univ. of Bologna, Italy), Paul Marchal (IMEC, Belgium), Luca Benini (Univ. of Bologna, Italy)
Page	pp. 914 - 919
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9B-5 (Time: 17:40 - 18:05)

Title	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
Author	*Yuchun Ma, Zhuoyuan Li (Tsinghua Univ., China), Jason Cong (Univ. of California, Los Angeles, United States), Xianlong Hong (Tsinghua Univ., China), Glenn Reinman (Univ. of California, Los Angeles, United States), Sheqin Dong, Qiang Zhou (Tsinghua Univ., China)
Page	pp. 920 - 925
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Session 9C Satisfiability and Applications
Time: 16:00 - 18:05 Friday, January 26, 2007
Location: Room 414+415
Chairs: Jun Sawada (IBM, United States), Takashi Takenaka (NEC, Japan)

9C-1 (Time: 16:00 - 16:25)

Title	Multithreaded SAT Solving
Author	*Matthew Lewis, Tobias Schubert, Bernd Becker (Albert-Ludwigs-Univ. of Freiburg, Germany)
Page	pp. 926 - 931
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9C-2 (Time: 16:25 - 16:50)

Title	Trace Compaction using SAT-based Reachability Analysis
Author	*Sean Safarpour, Andreas Veneris, Hratch Mangassarian (Univ. of Toronto, Canada)
Page	pp. 932 - 937
Detailed information (abstract, keywords, etc)
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9C-3 (Time: 16:50 - 17:15)

Title	Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
Author	*Stefan Disch, Christoph Scholl (Univ. of Freiburg, Germany)
Page	pp. 938 - 943
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9C-4 (Time: 17:15 - 17:40)

Title	Fixing Design Errors with Counterexamples and Resynthesis
Author	*Kai-hui Chang, Igor L. Markov, Valeria Bertacco (Univ. of Michigan at Ann Arbor, United States)
Page	pp. 944 - 949
Detailed information (abstract, keywords, etc)
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Session 9D Designers' Forum Panel: Top 10 Design Issues
Time: 16:00 - 18:05 Friday, January 26, 2007
Location: Small Auditorium, 5F

9D-1

Title	(Panel Discussion) Top 10 Design Issues
Author	Organizer: Haruyuki Tago (Toshiba, Japan), Moderator: Peter Hofstee (IBM, United States), Panelists: Toshihiro Hattori (Renesas, Japan), Tadahiro Kuroda (Keio Univ., Japan), Toshinari Takayanagi (P.A. Semi, United States), Toshinori Sato (Kyushu Univ., Japan)
Detailed information (abstract, keywords, etc)

The 12th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 12th Asia and South Pacific Design Automation Conference
Technical Program