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Table of Contents
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Session 1A Parasitic Simulation and Modeling
Moderators: Dipanjan Gope - Intel Corp., Santa Clara, CA
Vikram Jandhyala - Univ. of Washington, Seattle, WA
1A.1
Stable and Compact Inductance Modeling of 3-D Interconnect Structures ...................................... 1
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh
1A.2
A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits ....... 7
Hao Yu, Yiyu Shi, Lei He, David Smart
1A.3
Fullwave Volumetric Maxwell Solver Using Conduction Modes ....................................................... 13
Salvador Ortiz, Roberto Suaya
Session 1B Post-Placement Optimization Techniques
Moderators: Hai Zhou - Northwestern Univ., Evanston, IL
Soheil Ghiasi - Univ. of California, Davis, CA
1B.1
Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss Using
Adjustable Robust Optimization ........................................................................................................... 19
Murari Mani, Ashish K. Singh, Michael Orshansky
1B.2
Optimal Useful Clock Skew Scheduling in the Presence of Variations Using
Robust ILP Formulations ....................................................................................................................... 27
Vaibhav Nawale, Thomas W. Chen
1B.3
State Re-Encoding for Peak Current Minimization ............................................................................ 33
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Session 1C Variation Modeling
Moderators: Linda Milor - Georgia Institute of Tech., Atlanta, GA
Yehea Ismail - Northwestern Univ., Evanston, IL
1C.1
A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering ............................ 39
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw
1C.2
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of
Process and Environmental Variability ................................................................................................ 47
Ken’ichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
1C.3
Practical Variation-Aware Interconnect Delay and Slew Analysis for
Statistical Timing Verification ............................................................................................................... 54
Xiaoji Ye, Peng Li and Frank Liu
1C.4
Analysis and Modeling of CD Variation for Statistical Static Timing ............................................... 60
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
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Session 1D Embedded Tutorial: From Dual to Multi to Many Core – Opportunities and
Challenges for Supporting the New Exponential
Moderator: Yehea Ismail - Northwestern Univ., Evanston, IL
1D.1
From Single Core to Multi-Core: Preparing for a New Exponential .............................................. 67
Jeff Parkhurst, John Darringer, Bill Grundmann
Session 2A Embedded Tutorial: UML and SystemC for Industrial ESL Design –
Basic Principles and Applications
Moderator: Grant E. Martin - Tensilica, Inc., Santa Clara, CA
2A.1
UML for ESL Design – Basic Principles, Tools, and Applications ................................................... 73
W. Mueller, A. Rosti, S. Bocchio, E. Riccobene, P. Scandurra, W. Dehaene, Y. Vanderperren
Session 2B Efficient Delay Test Generation
Moderators: Kartik Mohanram - Rice Univ., Houston, TX
Kee Sup Kim - Intel Corp., Sacramento, CA
2B.1
On Bounding the Delay of a Critical Path .......................................................................................... 81
Leonard Lee, Li-C. Wang
2B.2
A Delay Fault Model for At-Speed Fault Simulation and Test Generation .................................... 89
Irith Pomeranz, Sudhakar M. Reddy
2B.3
Efficient Boolean Characteristic Function for Fast Timed ATPG ................................................... 96
Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang
2B.4
Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts ....................... 100
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
Session 2C Power Grid Analysis and Design
Moderators: Frank Liu - IBM Corp., Austin, TX
Noel Menezes - Intel Corp., Hillsboro, OR
2C.1
Fast Decap Allocation Based on Algebraic Multigrid ....................................................................... 107
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2C.2
Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification .. 112
Nestoras Evmorfopoulos, Dimitris Karampatzakis, Georgios Stamoulis
2C.3
Importance of Volume Discretization of Single and Coupled Interconnects .................................. 119
Ahmed Shebaita, Dusan Petranovic, Yehea Ismail
2C.4
Handling Inductance in Early Power Grid Verification ................................................................... 127
Nahi H. Abdul Ghani, Farid N. Najm
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Session 2D Optimization Techniques for Different Target Technologies
Moderators: Rajeev Murgai - Fujitsu Labs. of America, Inc., Sunnyvale, CA
Victor Kravets - IBM Corp., Yorktown Heights, NY
2D.1
Mapping Arbitrary Logic Functions into Synchronous Embedded
Memories for area Reduction on FPGAs ............................................................................................ 135
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen D. Brown
2D.2
Factor Cuts ............................................................................................................................................ 143
Satrajit Chatterjee, Alan Mishchenko, Robert Brayton
2D.3
An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2
m
) ....................... 151
Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
2D.4
Cost-Aware Synthesis of Asynchronous Circuits Based on Partial Acknowledgement ................. 158
Yu Zhou, Danil Sokolov, Alex Yakovlev
Session 3A Placement and Floorplanning
Moderators: Patrick Groeneveld - Magma Design Automation, Inc., Santa Clara, CA
Ralph H. Otten - Eindhoven Univ. of Tech., Eindhoven, Netherlands
3A.1
A Revisit to Floorplan Optimization by Lagrangian Relaxation ...................................................... 164
Chuan Lin, Hai Zhou, Chris Chu
3A.2
Fast Wire Length Estimation by Net Bundling for Block Placement .............................................. 172
Tan Yan, Hiroshi Murata
3A.3
Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model ..................... 179
Peter Spindler, Frank M. Johannes
3A.4
A High-Quality Mixed-Size Analytical Placer Considering Preplaced
Blocks and Density Constraint ............................................................................................................ 187
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
Session 3B Digital and RF Test and Reliability
Moderators: Manuel d'Abreu - Advanced Micro Devices, Inc., Sunnyvale, CA
Rob Aitken - ARM, Sunnyvale, CA
3B.1
Testing Delay Faults in Asynchronous Handshake Circuits ............................................................. 193
Feng Shi, Yiorgos Makris
3B.2
A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects ............. 198
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
3B.3
Design Optimization for Single-Event Upset Robustness Using Simultaneous
Dual-VDD and Sizing Techniques ....................................................................................................... 204
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
3B.4
Enhanced Error Vector Magnitude (EVM) Measurements for Testing WLAN Transceivers ..... 210
Erkan Acar, Sule Ozev, Kevin B. Redmond
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Session 3C Statistical Timing Analysis
Moderators: Yaping Zhan - Advanced Micro Devices, Inc., Austin, TX
Yehea Ismail - Northwestern Univ., Evanston, IL
3C.1
A Linear-Time Approach for Static Timing Analysis Covering all Process Corners .................... 217
Sari Onaissi, Farid N. Najm
3C.2
A Framework for Statistical Timing Analysis Using Non-Linear Delay and Slew Models ........... 225
Sarvesh Bhardwaj, Praveen Ghanta, Sarma Vrudhula
3C.3
An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis .................. 231
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam,
Michael Orshansky, David Z. Pan
3C.4
A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis ........ 237
Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester
Session 3D Power and Performance Optimizations on System Level Design
Moderators: Allen C.H. Wu - Syntronix Corp., Hsinchu, Taiwan
David Atienza - EPFL/Complutense Univ., Lausanne, Switzerland
3D.1
Cache Miss Clustering for Banked Memory Systems ....................................................................... 244
O. Ozturk, G. Chen, M. Kandemir, M. Karakoy
3D.2
A Bitmask-Based Code Compression Technique for Embedded Systems ....................................... 251
Seok-Won Seong, Prabhat Mishra
3D.3
Allocation Cost Minimization for Periodic Hard Real-Time Tasks in
Energy-Constrained DVS Systems ...................................................................................................... 255
Jian-Jia Chen, Tei-Wei Kuo
3D.4
Application-Specific Customization of Parameterized FPGA Soft-Core Processors ..................... 261
David Sheldon, Rakesh Kumar, Roman Lysecky, Frank Vahid, Dean Tullsen
Session 4A Analog Simulation and Verification
Moderators: Joel Phillips - Cadence Berkeley Labs, Berkeley, CA
Luca Daniel - Massachusetts Institute of Tech., Cambridge, MA
4A.1
TP-PPV: Piecewise Nonlinear, Time-Shifted Oscillator Macromodel Extraction for
Fast, Accurate PLL Simulation ........................................................................................................... 269
Xiaolue Lai, Jaijeet Roychowdhury
4A.2
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets ........................... 275
Scott Little, Nicholas Seegmiller, David Walter, Chris Myers, Tomohiro Yoneda
4A.3
PPV-HB: Harmonic Balance for Oscillator/PLL Phase Macromodel ............................................. 283
Ting Mei, Jaijeet Roychowdhury
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Session 4B Self Adaptation and Physical Awareness in High-Level Synthesis
Moderators: Soheil Ghiasi - Univ. of California, Davis, CA
Taewhan Kim - Seoul National Univ., Seoul, Korea
4B.1
Loop Pipelining for High-Throughput Stream Computation Using Self-Timed Rings ................. 289
Gennette Gill, John Hansen, Montek Singh
4B.2
Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation ................... 297
Min Ni, Seda Ogrenci Memik
4B.3
Guaranteeing Performance Yield in High-Level Synthesis .............................................................. 303
W.-L. Hung, Xiaoxia Wu, Yuan Xie
Session 4C Advances in Performance Modeling for Interconnect and Memory
Moderators: Emrah Acar - IBM Corp., Yorktown Heights, NY
Peng Li - Texas A&M Univ, College Station, TX
4C.1
Information Theoretic Approach to Address Delay and Reliability in
Long On-Chip Interconnects ............................................................................................................... 310
Rohit Singhal, Gwan Choi, Rabi Mahapatra
4C.2
Analytical Modeling of SRAM Dynamic Stability ............................................................................. 315
Bin Zhang, Ari Arapostathis, Sani Nassif, Michael Orshansky
4C.3
A High-Level Compact Pattern-Dependent Delay Model for High-Speed
Point-to-Point Interconnects ................................................................................................................ 323
Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
Session 4D Embedded Tutorial: Design and CAD Challenges in 45nm
CMOS and Beyond – From Front to Back
Moderator: David Kung – IBM Corp., Yorktown Heights, NY
4D.1
Design and CAD Challenges in 45nm CMOS and Beyond ............................................................... 329
David J. Frank, Ruchir Puri, Dorel Toma
Session 5A Analog Design Automation Techniques
Moderators: Ranga Vemuri - Univ. of Cincinnnati, Cincinnnati, OH
Yehia Massoud - Rice Univ., Houston, TX
5A.1
Robust System Level Design with Analog Platforms ......................................................................... 334
F. De Bernardinis, P. Nuzzo, A. Sangiovanni Vincentelli
5A.2
Template-Based Parasitic-Aware Optimization and Retargeting of
Analog and RF Integrated Circuit Layouts ........................................................................................ 342
Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi
5A.3
Analog Placement with Symmetry and Other Placement Constraints ............................................ 349
Yiu-Cheong Tam, Evangeline F.Y. Young, Chris Chu
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Session 5B Challenges on System Level Interconnection
Moderators: Margarida Jacome - Univ. of Texas, Austin, TX
Roman Hermida - Universidad Complutense de Madrid, Madrid, Spain
5B.1
Designing Application-Specific Networks on Chips with Floorplan Information .......................... 355
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta,
Luca Benini, Giovanni De Micheli, Luigi Raffo
5B.2
Fast and Accurate Transaction Level Models Using Result Oriented Modeling ............................ 363
Gunar Schirner, Rainer Dömer
5B.3
Optimal Memoryless Encoding for Low Power Off-Chip Data Buses ............................................. 369
Yeow Meng Chee, Charles J. Colbourn, Alan C.H. Ling
Session 5C Placement Optimization: Timing, Noise, and Power
Moderators: Hai Zhou - Northwestern Univ., Evanston, IL
John Lillis - Univ. of Illinois, Chicago, IL
5C.1
A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs ........................ 375
Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar
5C.2
Timing-Driven Placement for Heterogeneous Field Programmable Gate Array ........................... 383
Bo Hu
5C.3
Voltage Island Aware Floorplanning for Power and Timing Optimization .................................... 389
Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
5C.4
Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction .............................. 395
Eric Wong, Jacob Minz, Sung Kyu Lim
Session 5D Timing and Power Analysis
Moderators: Noel Menezes - Intel Corp., Hillsboro, OR
Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN
5D.1
A Timing Dependent Power Estimation Framework Considering Coupling .................................. 401
Debjit Sinha, DiaaEldin Khalil, Yehea Ismail, Hai Zhou
5D.2
Algorithms for MIS Vector Generation and Pruning ....................................................................... 408
Kenneth S. Stevens, Florentin Dartu
5D.3
Timing Model Reduction for Hierarchical Timing Analysis ............................................................ 415
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald Graham, Mike Hutton, Chung-Kuan Cheng
5D.4
A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power .......... 423
Sean X. Shi, Peng Yu, David Z. Pan
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Session 6A Thermal and Variability Issues in Architectures
Moderators: Elaheh Bozorgzadeh - Univ. of California, Irvine, CA
Tim Tuan - Xilinx Research, San Jose, CA
6A.1
Microarchitecture Parameter Selection to Optimize System Performance
Under Process Variation ...................................................................................................................... 429
Xiaoyao Liang, David Brooks
6A.2
Thermal Sensor Allocation and Placement for Reconfigurable Systems ......................................... 437
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik
6A.3
Thermal Characterization and Optimization in Platform FPGAs ................................................... 443
Priya Sundararajan, Aman Gayasen, N. Vijaykrishnan, T. Tuan
6A.4
Performance Analysis of Concurrent Systems with Early Evaluation ............................................ 448
Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky
Session 6B Embedded Tutorial: Automation in Mixed-Signal Design –
Reality Check and the Nano Challenge
Moderator: Georges Gielen - Katholieke Univ., Leuven, Belgium
6B.1
Near-Term Industrial Perspective of Analog CAD ........................................................................... 456
Christopher Labrecque
6B.2
Design Automation for Analog: The Next Generation of Tool Challenges ..................................... 458
Rob A. Rutenbar
6B.3
Automation in Mixed-Signal Design: Challenges and Solutions in the Wake of the Nano Era ..... 461
Trent McConaghy, Georges Gielen
Session 6C Global Routing
Moderators: Charles Chiang - Synopsys, Inc., Mountain View, CA
Mustafa Ozdal - Intel Corp., Hillsboro, OR
6C.1
FastRoute: A Step to Integrate Global Routing into Placement ....................................................... 464
Min Pan, Chris Chu
6C.2
Trunk Decomposition Based Global Routing Optimization ............................................................. 472
Devang Jariwala, John Lillis
6C.3
Optimizing Yield in Global Routing ................................................................................................... 480
Dirk Müller
6C.4
Wire Density Driven Global Routing for CMP Variation and Timing ............................................ 487
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
Session 6D Emerging Topics in Signal Integrity and Reliability
Moderators: Syed Alam - Freescale Semiconductor, Inc., Austin, TX
Vinod Kariat - Cadence Design Systems, Inc., San Jose, CA
6D.1
An Analytical Model for Negative Bias Temperature Instability ..................................................... 493
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
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6D.2
Soft Error Derating Computation in Sequential Circuits ................................................................. 497
Hossein Asadi, Mehdi B. Tahoori
6D.3
Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection ......... 502
Rajeev R. Rao, David Blaauw, Dennis Sylvester
6D.4
Current Path Analysis for Electrostatic Discharge Protection ......................................................... 510
Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu,
Yao-Wen Chang, Sy-Yen Kuo
Session 7A Fault-Tolerant Energy Minimization Techniques for Real-Time Embedded Systems
Moderators: Luca Carloni - Columbia Univ., New York, NY
Sheldon Tan - Univ. of California, Riverside, CA
7A.1
System-Wide Energy Minimization for Real-Time Tasks: Lower Bound and Approximation .... 516
Xiliang Zhong, Cheng-Zhong Xu
7A.2
Online Task-Scheduling for Fault-Tolerant Low-Energy Real-Time Systems ............................... 522
Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang
7A.3
Energy Management for Real-Time Embedded Systems with Reliability Requirements ............. 528
Dakai Zhu, Hakan Aydin
Session 7B Emerging Issues in Contemporaneous System Level Design
Moderators: Giovanni De Micheli - EPFL, Lausanne, Switzerland
Mike J. Wirthlin - Bringham Young Univ., Provo, UT
7B.1
Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design ................................... 535
Shuo Wang, Lei Wang
7B.2
System-Level Process-Driven Variability Analysis for Single and
Multiple Voltage-Frequency Island Systems ...................................................................................... 541
Diana Marculescu, Siddharth Garg
7B.3
Physical Aware Frequency Selection for Dynamic Thermal Management in
Multi-Core Systems .............................................................................................................................. 547
Rajarshi Mukherjee, Seda Ogrenci Memik
Session 7C Clock and Buffer Synthesis
Moderators: Patrick Groeneveld - Magma Design Automation, Inc., Santa Clara, CA
Ting-Chi Wang - National Tsing Hua Univ., Hsinchu, Taiwan
7C.1
A New RLC Buffer Insertion Algorithm ............................................................................................ 553
Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
7C.2
Clock Buffer Polarity Assignment for Power Noise Reduction ........................................................ 558
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
7C.3
Combinatorial Algorithms for Fast Clock Mesh Optimization ........................................................ 563
Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
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Session 7D Thermal Analysis for the Nano Scale
Moderators: Igor Keller - Cadence Design Systems, Inc., San Jose, CA
Masanori Hashimoto - Osaka Univ., Osaka, Japan
7D.1
An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation
Methodology for Leakage Dominant Technologies with Implications for Power
Estimation and Hot-Spot Management ............................................................................................... 568
Sheng-Chih Lin, Kaustav Banerjee
7D.2
Adaptive Multi-Domain Thermal Modeling and Analysis for
Integrated Circuit Synthesis and Design ............................................................................................ 575
Yonghong Yang, Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick
7D.3
Leakage Power Dependent Temperature Estimation to Predict
Thermal Runaway in FinFET Circuits ............................................................................................... 583
Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
Session 8A Advances in Embedded System Design
Moderators: Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA
Frank Vahid – Univ. of California, Riverside, CA
8A.1
Runtime Distribution-Aware Dynamic Voltage Scaling ................................................................... 587
Sungpack Hong, Sungjoo Yoo, Hoonsang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
8A.2
Formal Model of Data Reuse Analysis for Hierarchical Memory Organizations ........................... 595
Ilie I. Luican, Hongwei Zhu, Florin Balasa
8A.3
An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems ... 601
Chin-Hsien Wu, Tei-Wei Kuo
Session 8B Architectural Design Techniques for High Performance and Robustness
Moderators: Kanak B. Agarwal - IBM Corp., Austin, TX
Nam Sung Kim - Intel Corp., Hillsboro, OR
8B.1
Design and Integration Methods for a Multi-Threaded Dual Core 65nm Xeon® Processor ........ 607
Raj Varada, Mysore Sriram, Kris Chou, James Guzzo
8B.2
Counterflow Pipelining: Architectural Support for Preemption in
Asynchronous Systems Using Anti-Tokens ........................................................................................ 611
Manoj Ampalam, Montek Singh
8B.3
A New Paradigm for Low-Power, Variation-Tolerant Circuit Synthesis
Using Critical Path Isolation ................................................................................................................ 619
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
Session 8C Manufacturability and Power in Layout
Moderators: Jeng-Liang Tsai - Synopsys, Inc., Santa Clara, CA
Jiang Hu - Texas A&M Univ., College Station, TX
8C.1
Efficient Process-Hotspot Detection Using Range Pattern Matching .............................................. 625
H. Yao, S. Sinha, C. Chiang, X. Hong, Y. Cai
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8C.2
Post-Routing Redundant via Insertion and Line End Extension with via Density Consideration ... 633
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
8C.3
Post-Placement Voltage Island Generation ........................................................................................ 641
Royce L.S. Ching, Evangeline F.Y. Young, Kevin C.K. Leung, Chris Chu
Session 8D Embedded Tutorial: Emerging Nanoelectronics – Prospects,
State of the Art and Opportunities for CAD
Moderator: Margarida Jacome - Univ. of Texas, Austin, TX
8D.1
Prospects for Emerging Nanoelectronics in Mainstream Information Processing Systems .......... 647
Jeffrey Bokor
8D.2
Carbon Nanotube for Potential Electronic and Optoelectronic Applications ................................. 649
Jia Chen
8D.3
Carbon Nanotube Transistor Circuits – Models and Tools for
Design and Performance Optimization ............................................................................................... 651
H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan
Session 9A Technology Driven Layout Methodologies
Moderators: Duane S. Boning - Massachusetts Institute of Tech., Cambridge, MA
Lars W. Liebmann - IBM Corp., Hopewell Junction, NY
9A.1
Technology Migration Techniques for Simplified Layouts with Restrictive Design Rules ............ 655
Xiaoping Tang, Xin Yuan
9A.2
Fill for Shallow Trench Isolation CMP ............................................................................................... 661
Andrew B Kahng, Puneet Sharma, Alexander Zelikovsky
9A.3
An Optimal Simultaneous Diode/Jumper Insertion Algorithm for Antenna Fixing ...................... 669
Zhe-Wei Jiang, Yao-Wen Chang
Session 9B Novel FPGA Architectures, Techniques and Designs
Moderators: Lei He - Univ. of California, Los Angeles, CA
Michael Orshansky - Univ. of Texas, Austin, TX
9B.1
Performances Improvement of FPGA Using Novel Multilevel
Hierarchical Interconnection Structure .............................................................................................. 675
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
9B.2
Un/DoPack: Re-Clustering of Large System-on-Chip Designs with
Interconnect Variation for Low-Cost FPGAs .................................................................................... 680
Marvin Tom, David Leong, Guy Lemieux
9B.3
Studying a GALS FPGA Architecture Using a Parameterized Automatic Design Flow ............... 688
Xin Jia, Ranga Vemuri
9B.4
Conjoining Soft-Core FPGA Processors ............................................................................................. 694
David Sheldon, Rakesh Kumar, Frank Vahid, Dean Tullsen, Roman Lysecky
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Session 9C Specification and Architecture Challenges in High-Level Synthesis
Moderators: Robert P. Dick - Northwestern Univ., Evanston, IL
Wolfgang Rosenstiel - Univ. of Tuebingen, Tuebingen, Germany
9C.1
High-Level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor .... 702
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
9C.2
Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture ............. 709
Jason Cong, Yiping Fan, Wei Jiang
9C.3
A Code Refinement Methodology for Performance-Improved Synthesis from C .......................... 716
Greg Stitt, Frank Vahid, Walid Najjar
9C.4
Leveraging Protocol Knowledge in Slack Matching .......................................................................... 724
Girish Venkataramani, Seth C. Goldstein
Session 9D Defect Tolerance for Nanoscale Architectures
Moderators: Andre M. DeHon - Univ. of Pennsylvania, Philadelphia, PA
Iris Bahar - Brown Univ., Providence, RI
9D.1
Application-Independent Defect-Tolerant Crossbar Nano-Architectures ...................................... 730
Mehdi B. Tahoori
9D.2
Nanowire Addressing with Randomized-Contact Decoders ............................................................. 735
Eric Rachlin, John E. Savage
9D.3
On the Use of Bloom Filters for Defect Maps in Nanocomputing .................................................... 743
Gang Wang, Wenrui Gong, Ryan Kastner
Session 10A Dynamic Power Management
Moderators: Nikil Dutt - Univ. of California, Irvine, CA
Ryan Kastner – Univ. of California, Santa Barbara, CA
10A.1
Dynamic Power Management Using Machine Learning ................................................................... 747
Gaurav Dhiman, Tajana Simunic Rosing
10A.2
Dynamic Voltage and Frequency Management Based on Variable
Update Intervals for Frequency Setting .............................................................................................. 755
M. Najibi, M. Salehi, A. Afzali Kusha, M. Pedram, S.M. Fakhraie, H. Pedram
10A.3
Temperature-Aware Leakage Minimization Technique for Real-Time Systems ........................... 761
Lin Yuan, Sean Leventhal, Gang Qu
10A.4
Energy Budgeting for Battery-Powered Sensors with a Known Task Schedule ............................. 765
Daler Rakhmatov
Session 10B Advances in Model Checking
Moderators: Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI
Vigyan Singhal - Oski Technology, Fremont, CA
10B.1
Stepping Forward with Interpolants in Unbounded Model Checking ............................................ 772
Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer
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10B.2
Decomposing Image Computation for Symbolic Reachability Analysis
Using Control Flow Information ......................................................................................................... 779
David Ward, Fabio Somenzi
10B.3
Automatic Memory Reductions for RTL Model Verification .......................................................... 786
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
10B.4
Accelerating High-Level Bounded Model Checking .......................................................................... 794
Malay K. Ganai, Aarti Gupta
Session 10C Novel Interconnect Methodologies
Moderators: Nagib Z. Hakim - Intel Corp., Santa Clara, CA
Yu Kevin Cao - Arizona State Univ., Tempe, AZ
10C.1
Simultaneous Power and Thermal Integrity Driven via Stapling in 3D ICs ................................... 802
Hao Yu, Joanna Ho, Lei He
10C.2
Yield Prediction for 3D Capacitive Interconnections ........................................................................ 809
A. Fazzi, L. Magagni, M. De Dominicis, P. Zoffoli, R. Canegallo, P.L. Rolandi,
A. Sangiovanni-Vincentelli, R. Guerrieri
10C.3
Layer Minimization of Escape Routing in Area Array Packaging .................................................. 815
Renshen Wang, Rui Shi, Chung-Kuan Cheng
10C.4
Network Coding for Routability Improvement in VLSI ................................................................... 820
Nikhil Jayakumar, Kanupriya Gulati, Sunil P. Khatri, Alexander Sprintson
Session 10D Embedded Tutorial: Integrating Nanoelectronics, Biotechnology and MEMS/NEMS
Moderator: Margarida Jacome - Univ. of Texas, Austin, TX
10D.1
From Micro to Nano: MEMS as an Interface to the Nano World ................................................... 824
Bernhard E. Boser
10D.2
CMOS-MEMS Integration: Why, How and What? .......................................................................... 826
Ann Witvrouw
10D.3
Information Processing in Nanoscale Arrays: DNA Assembly,
Molecular Devices, Nano-Array Architectures .................................................................................. 828
Richard A. Kiehl
10D.4
Molecular Organic Electronic Circuits ............................................................................................... 830
Vladimir Bulović, Ioannis Kymissis, Ivan Nausieda, Kevin Ryu, Annie Wang,
Akintunde Ibitayo Akinwande, Charles G. Sodini
10D.5
Organic Electronic Device Modeling at the Nanoscale ...................................................................... 832
Conor Madigan, Vladimir Bulović
Session 11A Embedded Tutorial: Variability and Yield Improvement:
Rules, Models, and Characterization
Moderator: Sani Nassif - IBM Corp.,
11A.1
Variability and Yield Improvement: Rules, Models, and Characterization ................................... 834
K.L. Shepard, D.N. Maynard
Page 13
Session 11B Accelerating Verification
Moderators: Fabio Somenzi - Univ. of Colorado, Boulder, CO
Pete Manolios - Georgia Institute of Tech., Atlanta, GA
11B.1
Improvements to Combinational Equivalence Checking .................................................................. 836
Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, Niklas Een
11B.2
SMT(CLU): A Step toward Scalability in System Verification ........................................................ 844
Hossein M. Sheini, Karem A. Sakallah
11B.3S
Solving the Minimum-Cost Satisfiability Problem Using SAT
Based Branch-and-Bound Search ....................................................................................................... 852
Zhaohui Fu, Sharad Malik
11B.4S
Verification Through the Principle of Least Astonishment .............................................................. 860
Beth Isaksen, Valeria Bertacco
Session 11C Model Order Reduction and Parametric Analysis
Moderators: Janet M. Wang - Univ. of Arizona, Tucson, AZ
Ramachandra Achar - Carleton Univ., Ottawa, Canada
11C.1
Performance-Oriented Statistical Parameter Reduction of Parameterized
Systems via Reduced Rank Regression ............................................................................................... 868
Zhuo Feng, Peng Li
11C.2
Faster, Parametric Trajectory-Based Macromodels via Localized Linear Reductions ................. 876
Saurabh K. Tiwary, Rob A. Rutenbar
11C.3
Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty .................... 884
Wei-Shen Wang, Michael Orshansky
Session 11D Design and Modeling of Molecular-Scale Systems
Moderators: Chris Dwyer - Duke Univ., Durham, NC
Kaustav Banerjee – Univ. of California, Santa Barbara, CA
11D.1
From Molecular Interactions to Gates: A Systematic Approach ..................................................... 891
Josep Carmona, Jordi Cortadella, Yousuke Takada, Ferdinand Peper
11D.2
A Spectrally Accurate Integral Equation Solver for Molecular Surface Electrostatics ................. 899
Shih-Hsien Kuo, Jacob White
11D.3
Using CAD to Shape Experiments in Molecular QCA ...................................................................... 907
Michael Niemier, Michael Crocker, X. Sharon Hu, Marya Lieberman