CODES+ISSS'08 Table of Contents

Message from the Technical Program Chairs
Cathy Gebotys 
Grant Martin 

Organization

Author Index

Session 1A: Analysis of Parallel Application and Architecture Synthesis
Session Chair: Sungjoo Yoo (POSTECH)
Session Co-Chair: Grant Martin (Tensilica)

Synthesis of Heterogeneous Pipelined Multiprocessor Systems using ILP : JPEG Case Study (Page 1)
Haris Javaid (University of New South Wales)
Sri Parameswaran (University of New South Wales)

Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design (Page 7)
Giovanni Beltrame (European Space Agency)
Luca Fossati (Politecnico di Milano)
Donatella Sciuto (Politecnico di Milano)

Session 1B: Flash Memory Management
Session Chair: Hiroyuki Tomiyama (Nagoya University)
Session Co-Chair: Miguel Miranda (IMEC)

A Time-Predictable System Initialization Design for Huge-Capacity Flash-Memory Storage Systems (Page 13)
Chin-Hsien Wu (National Taiwan University of Science and Technology)

Deterministic Service Guarantees for NAND Flash Using Partial Block Cleaning (Page 19)
Siddharth Choudhuri (University of California at Irvine)
Tony Givargis (University of California at Irvine)

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Session 2A: Application Specific Processor Systems 
Session Chair: Sri Parameswaran (University of New South Wales)
Session Co-Chair: Grant Martin (Tensilica)

Static Analysis of Processor Stall Cycle Aggregation (Page 25)
Jongeun Lee (Arizona State University)
Aviral Shrivastava (Arizona State University)

Application Specific Non-Volatile Primary Memory for Embedded Systems (Page 31)
Kwangyoon Lee (University of California at San Diego)
Alex Orailoglu (University of California at San Diego)

Scratchpad Allocation for Concurrent Embedded Software (Page 37)
Vivy Suhendra (National University of Singapore)
Abhik Roychoudhury (National University of Singapore)
Tulika Mitra (National University of Singapore)

Software Optimization for MPSoC : A MPEG-2 Decoder Case Study (Page 43)
Eric Cheung (University of California at Riverside)
Harry Hsieh (University of California at Riverside)
Felice Balarin (Cadence Design Systems)

Session 2B: Performance Enhancement—New Techniques for FPGAs and Partitioning 
Session Chair: Reinaldo Bergamaschi (CadComponents, USA)
Session Co-Chair: Karam S. Chatha (Arizona State University)

Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits (Page 49)
Lance Saldanha (University of Arizona)
Roman Lysecky (University of Arizona)

A Performance-Oriented Hardware/Software Partitioning for Datapath Applications (Page 55)
Laura Frigerio (Politecnico di Milano)
Fabio Salice (Politecnico di Milano)

Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (Page 61)
Greg Stitt (University of Florida)
Gaurav Chaudhari (University of Florida)
James Coole (University of Florida)

Specification and OS-Based Implementation of Self-adaptive, Hardware / Software Embedded Systems (Page 67)
Yvan Eustache (Université Européenne de Bretagne)
Jean-Philippe Diguet (Université Européenne de Bretagne)

Session 3A: Multiprocessor and MPSoC Architectures 
Session Chair: Soon-Hoi Ha (Seoul National University)
Session Co-Chair: Donatella Sciuto (Politecnico di Milano)

Distributed and Low-Power Synchronization Architecture for Embedded Multiprocessors (Page 73)
Chenjie Yu (University of Maryland)
Peter Petrov (University of Maryland)

LOCS: A Low Overhead Profiler-Driven Design Flow for Security of MPSoCs (Page 79)
Krutartha Patel (The University of New South Wales)
Sri Parameswaran (The University of New South Wales)

Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (Page 85)
Jianguo Yao (McGill University)
Xue Liu (McGill University)
Mingxuan Yuan (Hong Kong University of Science and Technology)
Zonghua Gu (Hong Kong University of Science and Technology)

Intra- and Inter-Processor Hybrid Performance Modeling for MPSoC Architectures (Page 91)
Frank E. B. Ophelders (Technische Universiteit Eindhoven)
Samarjit Chakraborty (National University of Singapore)
Henk Corporaal (Technische Universiteit Eindhoven)

Session 3B: Exploration, Profiling and Tuning of Embedded Systems 
Session Chair: Grant Martin (Tensilica)
Session Co-Chair: Scott A. Mahlke (University of Michigan)

Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm (Page 97)
Chen Huang (University of California at Riverside)
David Sheldon (University of California at Riverside)
Frank Vahid (University of California at Riverside)

Static Analysis for Fast and Accurate Design Space Exploration of Caches (Page 103)
Yun Liang (National University of Singapore)
Tulika Mitra (National University of Singapore)

Profiling of Lossless-Compression Algorithms for a Novel Biomedical-Implant Architecture (Page 109)
Christos Strydis (Delft University of Technology)
Georgi N. Gaydadjiev (Delft University of Technology)

Holistic Design and Caching in Mobile Computing (Page 115)
Mwaffaq Otoom (Virginia Polytechnic Institute and State University)
JoAnn M. Paul (Virginia Polytechnic Institute and State University)

SPECIAL SESSION I: You Can Catch More Bugs with Transaction-Level Honey 
Session Organizer and Chair: Adam Donlin (Xilinx)

You Can Catch More Bugs With Transaction Level Honey (Page 121)
Miron Abramovici (DAFCA)
Kees Goossens (NXP Semiconductor)
Bart Vermeulen (NXP Semiconductor)
Jack Greenbaum (Greenhills Software)
Neal Stollon (HDL Dynamics)
Adam Donlin (Xilinex Research)

Session 5A: Simulation and Verification of Embedded Systems 
Session Chair: Don Thomas (Carnegie Mellon University)
Session Co-Chair: Franco Fummi (University of Verona)

Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (Page 125)
J. P. Grossman (D. E. Shaw Research)
Cliff Young (D. E. Shaw Research)
Joseph A. Bank (D. E. Shaw Research and Reservoir Labs)
Kenneth Mackenzie (D. E. Shaw Research and Reservoir Labs)
Douglas J. Ierardi (D. E. Shaw Research)
John K. Salmon (D. E. Shaw Research)
Ron O. Dror (D. E. Shaw Research)
David E. Shaw (D. E. Shaw Research)

Model Checking SystemC Designs Using Timed Automata (Page 131)
Paula Herber (Technical University of Berlin)
Joachim Fellmuth (Technical University of Berlin)
Sabine Glesner (Technical University of Berlin)

Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors (Page 137)
Heon-Mo Koo (Intel Corporation)
Prabhat Mishra (University of Florida)

Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (Page 143)
Matthias Krause (Forschungszentrum Informatik)
Dominik Englert (Forschungszentrum Informatik)
Oliver Bringmann (Forschungszentrum Informatik)
Wolfgang Rosenstiel (Forschungszentrum Informatik and Universität Tübingen)

Session 5B: Case Studies and Industrial Practices 
Session Chair: Tony Givargis (University of California at Irvine)
Session Co-Chair: Robert Walker (Kent State University)

Cache-aware Optimization of BAN Applications (Page 149)
Yun Liang (National University of Singapore)
Lei Ju (National University of Singapore)
Samarjit Chakraborty (National University of Singapore)
Tulika Mitra (National University of Singapore)
Abhik Roychoudhury (National University of Singapore)

Don't Forget Memories — A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs (Page 155)
David Sheldon (University of California at Riverside)
Frank Vahid (University of California at Riverside)

Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (Page 161)
Simon Schliecker (Technische Universität Braunschweig)
Mircea Negrean (Technische Universität Braunschweig)
Gabriela Nicolescu (Ecole Polytechnique de Montreal)
Pierre Paulin (ST Microelectronics)
Rolf Ernst (Technische Universität Braunschweig)

Extending Open Core Protocol to Support System-Level Cache Coherence (Page 167)
Konstantinos Aisopos (Princeton University)
Chien-Chun Chou (Sonics Inc.)
Li-Shiuan Peh (Princeton University)

Session 6A: Models and Techniques for Performance Estimation and Solution Space Representation, and a Special Citation Analysis 
Session Chair: Sudeep Pasricha (Colorado State University)
Session Co-Chair: Joerg Henkel (University of Karlsruhe)

Performance Debugging of Esterel Specifications (Page 173)
Lei Ju (National University of Singapore)
Bach Khoa Huynh (National University of Singapore)
Abhik Roychoudhury (National University of Singapore)
Samarjit Chakraborty (National University of Singapore)

SPaC: A Symbolic Pareto Calculator (Page 179)
Hamid Shojaei (Eindhoven University of Technology)
Twan Basten (Eindhoven University of Technology)
Marc Geilen (Eindhoven University of Technology)
Phillip Stanley-Marbell (Eindhoven University of Technology)

Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (Page 185)
Simon Schliecker (Technical University of Braunschweig)
Jonas Rox (Technical University of Braunschweig)
Matthias Ivers (Technical University of Braunschweig)
Rolf Ernst (Technical University of Braunschweig)

Highly-Cited Ideas in System Codesign and Synthesis (Page 191)
Frank Vahid (University of California at Riverside)
Tony Givargis (University of California at Irvine)

Session 6B: Advanced NoC Design Techniques 
Session Chair: Karam S. Chatha (Arizona State University)
Session Co-Chair: Petru Eles (Linkoping University)

A Security Monitoring Service for NoCs (Page 197)
Leandro Fiorin (University of Lugano)
Gianluca Palermo (Politecnico di Milano)
Cristina Silvano (Politecnico di Milano)

ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip (Page 203)
Huaxi Gu (Hong Kong University of Science and Technology)
Jiang Xu (Hong Kong University of Science and Technology)
Zheng Wang (Xidian University)

Asynchronous Transient Resilient Links for NoC (Page 209)
Simon Ogg (University of Southampton)
Bashir Al-Hashimi (University of Southampton)
Alex Yakovlev (Newcastle University)

Distributed Flit-Buffer Flow Control for Networks-on-Chip (Page 215)
Nicola Concer (Columbia University)
Michele Petracca (Columbia University)
Luca P. Carloni (Columbia University)

Keynote Address 
Session Chair: Catherine Gebotys (University of Waterloo)

Co-Design in the Wilderness (Page 221)
Dan Gale (CMC Microsystems)

SPECIAL SESSION II: Design and Defect Tolerance Beyond CMOS 
Session Organizer and Chair: X. Sharon Hu (University of Notre Dame)

Design and Defect Tolerance Beyond CMOS (Page 223)
Xiaobo Sharon Hu (University of Notre Dame)
Alexander Khitun (University of California at Los Angeles)
Konstantin K. Likharev (Stony Brook University)
Michael T. Niemier (University of Notre Dame)
Mingqiang Bao (University of California at Los Angeles)
Kang L. Wang (University of California at Los Angeles)

Session 8A: System Level Design: Throughput, Dependability, Coherence, and Yield 
Session Chair: Prabhat Mishra (University of Florida)
Session Co-Chair: Frank Vahid (University of California at Riverside)

Slack Analysis in the System Design Loop (Page 231)
Girish Venkataramani (Carnegie Mellon University)
Seth C. Goldstein (Carnegie Mellon University)

Symbolic Voter Placement for Dependability-Aware System Synthesis (Page 237)
Felix Reimann (University of Erlangen-Nuremberg)
Michael Glaß (University of Erlangen-Nuremberg)
Martin Lukasiewycz (University of Erlangen-Nuremberg)
Joachim Keinert (University of Erlangen-Nuremberg)
Christian Haubelt (University of Erlangen-Nuremberg)
Jürgen Teich (University of Erlangen-Nuremberg)

Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (Page 243)
Theo Kluter (Ecole Polytechnique Fédérale de Lausanne)
Philip Brisk (Ecole Polytechnique Fédérale de Lausanne)
Paolo Ienne (Ecole Polytechnique Fédérale de Lausanne)
Edoardo Charbon (Ecole Polytechnique Fédérale de Lausanne)

Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable MultiProcessors (Page 249)
Love Singhal (University of California at Irvine)
Sejong Oh (Korea Advanced Institute of Science and Technology)
Eli Bozorgzadeh (University of California at Irvine)

Session 8B: System Level Power Modeling and Optimization 
Session Chair: Ann Gordon-Ross (University of Florida)
Session Co-Chair: Roman Lysecky (University of Arizona)

Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (Page 255)
Young-Hwan Park (University of California at Irvine)
Sudeep Pasricha (Colorado State University)
Fadi J. Kurdahi (University of California at Irvine)
Nikil Dutt (University of California at Irvine)

Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (Page 261)
Michael A. Baker (Arizona State University)
Viswesh Parameswaran (Arizona State University)
Karam S. Chatha (Arizona State University)
Baoxin Li (Arizona State University)

Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (Page 267)
Gang Quan (University of South Carolina)
Yan Zhang (University of South Carolina)
William Wiles (University of South Carolina)
Pei Pei (University of South Carolina)

System-Level Mitigation of WID Leakage Power Variability Using Body-Bias Islands (Page 273)
Siddharth Garg (Carnegie Mellon University)
Diana Marculescu (Carnegie Mellon University)