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CODES+ISSS'08
Author Index
Abramovici, Miron
You Can Catch More Bugs With Transaction Level Honey (page 121)
Aisopos, Konstantinos
Extending Open Core Protocol to Support System-Level Cache Coherence (page 167)
Al-Hashimi, Bashir
Asynchronous Transient Resilient Links for NoC (page 209)
Baker, Michael A.
Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (page 261)
Balarin, Felice
Software Optimization for MPSoC : A MPEG-2 Decoder Case Study (page 43)
Bank, Joseph A.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
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Bao, Mingqiang
Design and Defect Tolerance Beyond CMOS (page 223)
Basten, Twan
SPaC: A Symbolic Pareto Calculator (page 179)
Beltrame, Giovanni
Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design (page 7)
Bozorgzadeh, Eli
Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable MultiProcessors (page 249)
Bringmann, Oliver
Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (page 143)
Brisk, Philip
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (page 243)
Carloni, Luca P.
Distributed Flit-Buffer Flow Control for Networks-on-Chip (page 215)
Chakraborty, Samarjit
Intra- and Inter-Processor Hybrid Performance Modeling for MPSoC Architectures (page 91)
Cache-aware Optimization of BAN Applications (page 149)
Performance Debugging of Esterel Specifications (page 173)
Charbon, Edoardo
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (page 243)
Chatha, Karam S.
Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (page 261)
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Chaudhari, Gaurav
Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (page 61)
Cheung, Eric
Software Optimization for MPSoC : A MPEG-2 Decoder Case Study (page 43)
Chou, Chien-Chun
Extending Open Core Protocol to Support System-Level Cache Coherence (page 167)
Choudhuri, Siddharth
Deterministic Service Guarantees for NAND Flash Using Partial Block Cleaning (page 19)
Concer, Nicola
Distributed Flit-Buffer Flow Control for Networks-on-Chip (page 215)
Coole, James
Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (page 61)
Corporaal, Henk
Intra- and Inter-Processor Hybrid Performance Modeling for MPSoC Architectures (page 91)
Diguet, Jean-Philippe
Specification and OS-Based Implementation of Self-adaptive, Hardware / Software Embedded Systems (page 67)
Donlin, Adam
You Can Catch More Bugs With Transaction Level Honey (page 121)
Dror, Ron O.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Dutt, Nikil
Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (page 255)
Englert, Dominik
Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (page 143)
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Ernst, Rolf
Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (page 161)
Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (page 185)
Eustache, Yvan
Specification and OS-Based Implementation of Self-adaptive, Hardware / Software Embedded Systems (page 67)
Fellmuth, Joachim
Model Checking SystemC Designs Using Timed Automata (page 131)
Fiorin, Leandro
A Security Monitoring Service for NoCs (page 197)
Fossati, Luca
Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design (page 7)
Frigerio, Laura
A Performance-Oriented Hardware/Software Partitioning for Datapath Applications (page 55)
Gale, Dan
Co-Design in the Wilderness (page 221)
Garg, Siddharth
System-Level Mitigation of WID Leakage Power Variability Using Body-Bias Islands (page 273)
Gaydadjiev, Georgi N.
Profiling of Lossless-Compression Algorithms for a Novel Biomedical-Implant Architecture (page 109)
Gebotys, Cathy
Message from the Technical Program Chairs
Geilen, Marc
SPaC: A Symbolic Pareto Calculator (page 179)
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Givargis, Tony
Deterministic Service Guarantees for NAND Flash Using Partial Block Cleaning (page 19)
Highly-Cited Ideas in System Codesign and Synthesis (page 191)
Glaß, Michael
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Glesner, Sabine
Model Checking SystemC Designs Using Timed Automata (page 131)
Goldstein, Seth C.
Slack Analysis in the System Design Loop (page 231)
Goossens, Kees
You Can Catch More Bugs With Transaction Level Honey (page 121)
Greenbaum, Jack
You Can Catch More Bugs With Transaction Level Honey (page 121)
Grossman, J. P.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Gu, Huaxi
ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip (page 203)
Gu, Zonghua
Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (page 85)
Haubelt, Christian
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Herber, Paula
Model Checking SystemC Designs Using Timed Automata (page 131)
Hsieh, Harry
Software Optimization for MPSoC : A MPEG-2 Decoder Case Study (page 43)
Hu, Xiaobo Sharon
Design and Defect Tolerance Beyond CMOS (page 223)
Huang, Chen
Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm (page 97)
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Huynh, Bach Khoa
Performance Debugging of Esterel Specifications (page 173)
Ienne, Paolo
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (page 243)
Ierardi, Douglas J.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Ivers, Matthias
Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (page 185)
Javaid, Haris
Synthesis of Heterogeneous Pipelined Multiprocessor Systems using ILP : JPEG Case Study (page 1)
Ju, Lei
Cache-aware Optimization of BAN Applications (page 149)
Performance Debugging of Esterel Specifications (page 173)
Keinert, Joachim
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Khitun, Alexander
Design and Defect Tolerance Beyond CMOS (page 223)
Kluter, Theo
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (page 243)
Koo, Heon-Mo
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors (page 137)
Krause, Matthias
Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (page 143)
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Kurdahi, Fadi J.
Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (page 255)
Lee, Jongeun
Static Analysis of Processor Stall Cycle Aggregation (page 25)
Lee, Kwangyoon
Application Specific Non-Volatile Primary Memory for Embedded Systems (page 31)
Li, Baoxin
Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (page 261)
Liang, Yun
Static Analysis for Fast and Accurate Design Space Exploration of Caches (page 103)
Cache-aware Optimization of BAN Applications (page 149)
Likharev, Konstantin K.
Design and Defect Tolerance Beyond CMOS (page 223)
Liu, Xue
Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (page 85)
Lukasiewycz, Martin
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Lysecky, Roman
Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits (page 49)
Mackenzie, Kenneth
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Marculescu, Diana
System-Level Mitigation of WID Leakage Power Variability Using Body-Bias Islands (page 273)
Martin, Grant
Message from the Technical Program Chairs
Mishra, Prabhat
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors (page 137)
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Mitra, Tulika
Scratchpad Allocation for Concurrent Embedded Software (page 37)
Static Analysis for Fast and Accurate Design Space Exploration of Caches (page 103)
Cache-aware Optimization of BAN Applications (page 149)
Negrean, Mircea
Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (page 161)
Nicolescu, Gabriela
Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (page 161)
Niemier, Michael T.
Design and Defect Tolerance Beyond CMOS (page 223)
Ogg, Simon
Asynchronous Transient Resilient Links for NoC (page 209)
Oh, Sejong
Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable MultiProcessors (page 249)
Ophelders, Frank E. B.
Intra- and Inter-Processor Hybrid Performance Modeling for MPSoC Architectures (page 91)
Orailoglu, Alex
Application Specific Non-Volatile Primary Memory for Embedded Systems (page 31)
Otoom, Mwaffaq
Holistic Design and Caching in Mobile Computing (page 115)
Palermo, Gianluca
A Security Monitoring Service for NoCs (page 197)
Parameswaran, Sri
Synthesis of Heterogeneous Pipelined Multiprocessor Systems using ILP : JPEG Case Study (page 1)
LOCS: A Low Overhead Profiler-Driven Design Flow for Security of MPSoCs (page 79)
Parameswaran, Viswesh
Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (page 261)
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Park, Young-Hwan
Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (page 255)
Pasricha, Sudeep
Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (page 255)
Patel, Krutartha
LOCS: A Low Overhead Profiler-Driven Design Flow for Security of MPSoCs (page 79)
Paul, JoAnn M.
Holistic Design and Caching in Mobile Computing (page 115)
Paulin, Pierre
Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (page 161)
Peh, Li-Shiuan
Extending Open Core Protocol to Support System-Level Cache Coherence (page 167)
Pei, Pei
Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (page 267)
Petracca, Michele
Distributed Flit-Buffer Flow Control for Networks-on-Chip (page 215)
Petrov, Peter
Distributed and Low-Power Synchronization Architecture for Embedded Multiprocessors (page 73)
Quan, Gang
Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (page 267)
Reimann, Felix
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Rosenstiel, Wolfgang
Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (page 143)
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Rox, Jonas
Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (page 185)
Roychoudhury, Abhik
Scratchpad Allocation for Concurrent Embedded Software (page 37)
Cache-aware Optimization of BAN Applications (page 149)
Performance Debugging of Esterel Specifications (page 173)
Saldanha, Lance
Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits (page 49)
Salice, Fabio
A Performance-Oriented Hardware/Software Partitioning for Datapath Applications (page 55)
Salmon, John K.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Schliecker, Simon
Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (page 161)
Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (page 185)
Sciuto, Donatella
Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design (page 7)
Shaw, David E.
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Sheldon, David
Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm (page 97)
Don't Forget Memories — A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs (page 155)
Shojaei, Hamid
SPaC: A Symbolic Pareto Calculator (page 179)
Shrivastava, Aviral
Static Analysis of Processor Stall Cycle Aggregation (page 25)
Silvano, Cristina
A Security Monitoring Service for NoCs (page 197)
Singhal, Love
Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable MultiProcessors (page 249)
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Stanley-Marbell, Phillip
SPaC: A Symbolic Pareto Calculator (page 179)
Stitt, Greg
Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (page 61)
Stollon, Neal
You Can Catch More Bugs With Transaction Level Honey (page 121)
Strydis, Christos
Profiling of Lossless-Compression Algorithms for a Novel Biomedical-Implant Architecture (page 109)
Suhendra, Vivy
Scratchpad Allocation for Concurrent Embedded Software (page 37)
Teich, Jürgen
Symbolic Voter Placement for Dependability-Aware System Synthesis (page 237)
Vahid, Frank
Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm (page 97)
Don't Forget Memories — A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs (page 155)
Highly-Cited Ideas in System Codesign and Synthesis (page 191)
Venkataramani, Girish
Slack Analysis in the System Design Loop (page 231)
Vermeulen, Bart
You Can Catch More Bugs With Transaction Level Honey (page 121)
Wang, Kang L.
Design and Defect Tolerance Beyond CMOS (page 223)
Wang, Zheng
ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip (page 203)
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Wiles, William
Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (page 267)
Wu, Chin-Hsien
A Time-Predictable System Initialization Design for Huge-Capacity Flash-Memory Storage Systems (page 13)
Xu, Jiang
ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip (page 203)
Yakovlev, Alex
Asynchronous Transient Resilient Links for NoC (page 209)
Yao, Jianguo
Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (page 85)
Young, Cliff
Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (page 125)
Yu, Chenjie
Distributed and Low-Power Synchronization Architecture for Embedded Multiprocessors (page 73)
Yuan, Mingxuan
Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (page 85)
Zhang, Yan
Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (page 267)
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