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Reconfigurable Architectures Workshop - RAW
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Workshop Introduction - RAW
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RAW Keynote 1: The Outer Limits: Reconfigurable Computing in Space and In Orbit
Maya Gokhale
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RAW Keynote 2: New Horizons of Very High Performance Computing (VHPC): Hurdles and Chances
Reiner Hartenstein
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Analysis of a Reconfigurable Network Processor
Christoforos Kachris, Stamatis Vassiliadis
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Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor
Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura , Hideharu Amano
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2D Defragmentation Heuristics for Hardware Multitasking on Reconfigurable Devices
Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero
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A Cost-Effective Context Memory Structure for Dynamically Reconfigurable Processors
Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano
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Performance of FPGA Implementation of Bit-split Architecture for Intrusion Detection Systems
Hong-jip Jung, Zachary K. Baker, Viktor K. Prasanna
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A Configuration Memory Hierarchy for Fast Reconfiguration with Reduced Energy Consumption Overhead
Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
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Maximum Edge Matching for Reconfigurable Computing
Markus Rullmann, Renate Merker
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FPGA Implementation of a License Plate Recognition SoC using Automatically Generated Streaming Accelerators
Nikolaos Bellas, Sek Chai, Malcolm Dwyer, Dan Linzmeier
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A High-level Target-precise Model for Designing Reconfigurable HW Tasks
Maik Boden, Steffen Ruelke, Jürgen Becker
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Rapid Development of High Performance Floating-Point Pipelines for Scientific Simulation
Gerhard Lienhart, Andreas Kugel, Reinhard Männer
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An Optimal Architecture for a DDC
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Smit
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Reconfigurable Memory Based AES Co-Processor
Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa
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Communication Concept for Adaptive Intelligent Run-Time Systems Supporting Distributed Reconfigurable Embedded Systems
Michael Ullmann, Jürgen Becker
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FPGA based Architecture for DNA Sequence Comparison and Database Search
Euripides Sotiriades, Christos Kozanitis, Apostolos Dollas
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Accelerating DTI Tractography using FPGAs
Aditya Kwatra, Viktor Prasanna, Manbir Singh
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An Adaptive System-on-Chip for Network Applications
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
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Dedicated Module Access in Dynamically Reconfigurable Systems
J. Hagemeyer, B. Kettelhoit, M. Porrmann
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Exploiting dynamic reconfiguration of platform FPGAs: Implementation issues
Miguel L. Silva, João Canas Ferreira
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A Distributed Object System Approach for Dynamic Reconfiguration
Ronald Hecht, Stephan Kubisch, Harald Michelsen, Elmar Zeeb, Dirk Timmermann
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Elementary Block Based 2-Dimensional Dynamic and Partial Reconfiguration for Virtex-II FPGAs
Michael Hübner, Christian Schuck, Jürgen Becker
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Physically-aware Exploitation of Component Reuse in a Partially Reconfigurable Architecture
Love Singhal, Elaheh Bozorgzadeh
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Partitioned Scheduling of Periodic Real-Time Tasks onto Reconfigurable Hardware
Klaus Danne, Marco Platzner
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A Pattern Selection Algorithm for Multi-Pattern Scheduling
Yuanqing Guo, Cornelis Hoede, Gerard J.m. Smit
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Mapping DSP Applications on Processor Systems with Coarse-Grain Reconfigurable Hardware
Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
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VoC: A Reconfigurable Matrix for Stereo Vision Processing
Ricardo Pezzuol Jacobi, Renato Barreto Cardoso, Geovany Borges
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Selection of Instruction Set Extensions for an FPGA Embedded Processor Core
Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones
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Dynamic Configuration Steering for a Reconfigurable Superscalar Processor
Nick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio
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Automatic Application-Specific Microarchitecture Reconfiguration
Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood
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Accelerating CABAC Encoding for Multi-standard Media with Configurability
Oskar Flordal, Di Wu, Dake Liu
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Exploiting Processing Locality through Paging Configurations in Multitasked Reconfigurable Systems
Mohamed Taher, Tarek El-Ghazawi
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Investigation into Programmability for Layer 2 Protocol Frame Delineation Architectures
Ciaran Toal, Sakir Sezer
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Multi-level Reconfigurable Architectures in the Switch Model
Sebastian Lange, Martin Middendorf
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Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications
Konstantinos Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
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Multi-Clock Pipelined Design of an IEEE 802.11a Physical Layer Transmitter
Maryam Mizani, Daler Rakhmatov
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On-chip and On-line Self-Reconfigurable Adaptable Platform: the Non-Uniform Cellular Automata Case
Andres Upegui, Eduardo Sanchez
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Increasing Analog Programmability in SoCs
Erik Schüler, Luigi Carro
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Partial and dynamic Reconfiguration of FPGAs : a top down design methodology for an automatic implementation
Florent Berthelot, Fabienne Nouvel, Dominique Houzet
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Architecture of a Multi-Context FPGA Using a hybrid Multiple-Valued/Binary Context Switching Signal
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
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A High Level SoC Power Estimation Based on IP Modeling
David Elleouet, Nathalie Julien, Dominique Houzet
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Implementation of a Reconfigurable Hard Real-Time Control System for Mechatronic and Automotive Applications
Steffen Toscher, Roland Kasper, Thomas Reinemann
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Run-Time Reconfiguration of Communication in SIMD Architectures
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter Jonker
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Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time
Sascha Uhrig, Stefan Maier, Georgi Kuzmanov, Theo Ungerer
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Reconfiguration of Embedded Java Applications
João Cláudio Soares Otero, Flávio Rech Wagner, Luigi Carro
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Speech Silicon AM: An FPGA-Based Acoustic Modeling Pipeline for Hidden Markov Model based Speech Recognition
Jeffrey W. Schuster, Raymond Hoare, Kshitij Gupta
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Implementation of a Programmable Array Processor Architecture for Approximate String Matching Algorithms on FPGAs
Panagiotis D. Michailidis, Konstantinos G. Margaritis
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ReConfigME: A Detailed Implementation of an Operating System for Reconfigurable Computing
Grant Wigley, David Kearney, Mark Jasiunas
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An Automated Development Framework for a RISC Processor with Reconfigurable Instruction Set Extensions
Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
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High-Level Synthesis with Reconfigurable Datapath Components
George Economakos
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An Optically Differential Reconfigurable Gate Array with a Holographic Memory
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
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A Stochastic Multi-Objective Algorithm for the Design of High Performance Reconfigurable Architectures
Wing On Fung, Tughrul Arslan
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Reconfigurable Communications for Image Processing Applications
André Borin Soares, Luigi Carro, Altamiro Amadeu Susin
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Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup
Kieran Mclaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias Noll, John McCanny
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RTOS Extensions for Dynamic Hardware / Software Monitoring and Configuration Management.
Yvan Eustache, Jean-Philippe Diguet, Milad El Khodary
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Securing Embedded Programmable Gate Arrays in Secure Circuits
Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frederic Bancel
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Design Space Exploration for Low-Power Reconfigurable Fabrics
Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
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Exploiting Dynamic Reconfiguration Techniques: The 2D-VLIW Approach
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
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Applying Single Processor Algorithms to Schedule Tasks on Reconfigurable Devices Respecting Reconfiguration Times
Florian Dittmann, Marcelo Götz
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Dynamically Reconfigurable Cache Architecture Using Adaptive Block Allocation Policy
Milene Barbosa Carvalho, Luís Fabrcio Wanderley Góes, Carlos Augusto Paiva Da Silva Martins
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Practical Design of a Computation and Energy Efficient Hardware Task Scheduler in Embedded Reconfigurable Computing Systems
Tyrone Tai-on Kwok, Yu-kwong Kwok
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Reconfigurable Context-Free Grammar Based Data Processing Hardware with Error Recovery
James Moscola, Young H. Cho, John W. Lockwood
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Power Consumption Advantage of a Dynamic Optically Reconfigurable Gate Array
Minoru Watanabe, Fuminori Kobayashi
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VHDL to FPGA automatic IPCore generation: A case study on Xilinx design flow
Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco Domenico Santambrogio
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