 |
U-BOOTH
CONTENT
System Exploration
SoC Architecture Explorer
Takeshi Shiro
University of Osaka - Japan
Mapping of Electronical System Level (ESL) Models into Implementation
Tommy Baumann, Horst Salzwedel
University of Ilmenau - Germany
YARDstick: Automation tool for custom processor development
Nikolaos Kavvadias, Spiridon Nikolaidis
University of Thessaloniki - Greece
TTool for DIPLODOCUS: An Environment for Design Space Exploration
Ludovic Apvrille
Ecole Nationale Supérieure des Télécommunications de Paris - France
MORPHEUS: Multi-purOSe dynamically Reconfigurable Platform for intensive HEterogeneoUS processing
Matthias Kühnle, Florian Thoma, Michael Hübner, Jürgen Becker
University of Karlsruhe - Germany
Performance Exploration with MLDesigner using Standardized Communication Interfaces
Tommy Baumann, Alexander Pacholik, Horst Salzwedel
University of Ilmenau - Germany
GRAPES System Explorer
Gianluca Palermo, Matteo Monchiero, Oreste Villa, Cristina Silvano
Politecnico di Milano - Italy
Fast Instruction Cache Analyzer Software Tool
Nikolaos Kroupis, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris
University of Thrace - Greece
High Level Synthesis
Comrade - A Compiler for Adaptative Systems
Hagen Gädke, Andreas Koch
University of Braunschweig - Germany
IMEM: A C++ High-Level Synthesis Tool for FPGA based Real-Time Video Processing Systems
Najeem Lawal, Benny Thörnberg, Mattias O’Nils
University of Sundsvall - Sweden
OSSS+R: Simulation and Synthesis of Self-Adaptative Systems
Philipp A. Hartmann, Andreas Schallenberg, Frank Oppenheimer, Wolfgang Nebel
OFFIS Institute - University of Oldenburg - Germany
Workcraft: A Static Data Flow Structure Editing, Visualisation and Analysis Tool
Ivan Poliakov, Danil Sokolov, Andrey Mokhov, Alex Yakovlev
University of Newcastle - United Kingdom
GAUT: High Level Synthesis - From C to RTL
Pierre Bomel
University de Bretagne Sud - France
UPAK: Abstract Unified Pattern Based Synthesis Kernel for Hardware and Software Systems
Christophe Wolinski, Krzysztof Kuchcinski, Adam Postula
University of Rennes - France
CandoGen: A Property-based Model Generator
Martin Schickel, Volker Nimbler, Martin Braun, Hans Eveking
University of Darmstadt - Germany
System Analysis Simulation & Verification
Enhancement of Statechart-Modelling: the Kiel Environment
Steffen Prochnow, Reinhard von Hanxleden
University of of Kiel - Germany
Performance Analysis of Tightly Coupled Multiprocessor Systems with SymTA/S
S. Schliecker, R.Henia, A. Hammann, R. Racu, J. Rox, M. Sebastian, S. Stein, R. Ernst
University of Braunschweig - Germany
DECIDER: Test and Verification at the Register-Transfer Level
Jaan Raik, Maksim Jenihhin, Raimund Ubar
University of Tallinn - Estonia
HIFSuite: Tools for HDL Code Manipulation
Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni
University of Verona – Italy
NEX : A Network Emulator boX to support the design of networked systems
Stefano Cailotto, Franco Fummi, Davide Quaglia, Walter Vendraminetto
University of Verona - Italy
OTAWA: Open Tool for Adaptative WCET Analysis
Hughes Cassé, Christine Rochange
University of Toulouse - France
Constraint Verification Using a Constraint Engineering System
André Schäfer, J. Freuer, K. Hahn, W. Nebel, R. Brück
University of Siegen - Germany
INTEREST (Integrating European Embedded Systems Tools)
Eric Bantegnie, Christian Ferdinand, Ulrich Freund, Paolo Gai, Marek Jersak, Dusan Kolar, Roman Pallierer
Esterel Technologies - Germany
SoC Platform
Rapid Industrial Prototyping Heterogenous Plate-form : 3G/4G Wireless Systems
Fabienne Nouvel, Arnaud Massiani, Christophe Le Guellaut
INSA de Rennes - France
RESUME’s Wavelet-Based Scalable Video Decoder
Hendrik Eeckhaut, Mark Christiaens, Harald Devos, Philippe Faes, Dirk Stroobandt
University of Ghent - Belgium
Light-Weight, Predictable Reactive Processing: the Kiel Esterel Processor
Xin Li, Reinhard von Hanxleden
University of Kiel - Germany
NoCRay, an FPGA Network-on-Chip based MP-SoC for Graphics Ray-tracing Applications
Sergio Tota, Mario Roberto Casu, Paolo Motto, Massimo Ruo Roch, Maurizio Zamboni
Politecnico di Torino - Italy
INDRA: Integrated Design Flow for Reconfigurable Architectures
Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann
University of Paderborn - Germany
Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks
Thorsten Jungeblut, Matthias Grünewald, Mario Porrmann, Ulrich Rückert
University of Paderborn - Germany
MOVES: A Tool for Modelling and Verification of Embedded Systems
J. Ellebaek, K. S. Knudsen, A. Brekling, M. R. Hansen, J. Madsen
University of Danemark - Danemark
FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications
Pascal Vivet, Didier Lattard, Fabien Clermidy, Edith Beigne, Christian Bernard, Yves Durand, Jean Durupt, Didier Varreau
CEA-LETI Grenoble - France
Design & Tools for FPGA
A Tool Flow for Design Space Exploration of Partially Re-configurable Processors
K. Karuri, A. Chattopadhyay, S. Kraemer, R. Leupers, G. Ascheid, H. Meyr
University of Aachen - Germany
Generalized Platform for Sensor Data Processing
D. Kriesten, M. Roessler, B. Berger, A. Fross, D. Fross, S. Goller, T. Leibelt, U. Heinkel
University of Chemnitz - Germany
Application-Domain Specific Reconfigurable FPGA Platform : An Integrated Hardware and Software Design Approach
Kostas Siozios, Dimitrios Soudris
University of Thrace - Greece
Transparent Object Integration in Distributed H/S Systems
F. Rincón, J. Barba, F. Moya, J. Dondo, D. Villa, F.J. Villanueva, J.C. López
University of Castilla-La Mancha - Spain
Partial Run-Time Reconfiguration Based on Distributed Objects
F. Rincón, J. Barba, F. Moya, J. Dondo, D. Villa, F.J. Villanueva, J.C. López
University of Castilla-La Mancha - Spain
The Demonstration of Low-power High-performance H.264 Decoder with Rapid SoC Prototyping Platform
Sangkwon Na, Woong Hwangbo, Jaemoon Kim, Sheunghan Lee, Chong-Min Kyung
Korea Advanced Institute of Science and Technology - South Korea
Partial Run-Time Reconfiguration of a Bit-Serial Architecture
Achim Rettberg, Florian Dittmann, Stefan Frank, Elmar Weber, Raphael Weber
University of Paderborn - Germany
Design of a Hardware Multiprocessor Real-Time Operating System
Fabrice Muller, Farooq Muhammad, Michel Auguin
University of Nice-Sophia Antipolis - France
SystemC
The VISION Project: SysXplorer (FZI)
Joachim Gerlach, Oliver Bringmann
Robert Bosch, FZI Forschungszentrum Informatik - Germany
UT SystemC Studio
Reihaneh Saberi, Amir Masoud Gharehbaghi, Parisa Razaghi, Anahita Naghilou, Zainalabedin Navabi
University of Tehran - Iran
UT Mixed-Signal Simulator
Hamidreza Ghasemi, Amir Masoud Gharehbaghi, Arezoo Kamran, Sheih Abolmaali, Zainalabedin Navabi
University of Tehran - Iran
SCope: SoC Co-simulation and Performance Estimation in SystemC
Héctor Posadas, David Quijano, Eugenio Villar, Marcos Martínez
University of Cantabria - Spain
SystemCoDesigner – The System Level Hardware-Software-Co-Design Tool
J. Falk, J. Gladigau, M. Glaß, C. Haubelt, S. Helwig, J. Keinert, M. Lukasiewycz, T. Schlichter, T. Streichert, M. Streubühr, J. Teich
University of Erlangen-Nuremberg - Germany
SoCBase-DE: A SystemC-based Multimedia System Design Environment
Sanggyu Park, Sangyong Yoon, Dosun Hong, Soo-Ik Chae
University of Seoul - South Korea
Visualized SystemC Debugging
Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke
University of Bremen/Fraunofer IIS - Germany
Mixed Signal + Hardware Solutions & Test
Data Converter BIST Development Tools
Ian Grout, Thomas O’Shea, Jeffrey Ryan
University of Limerick - Ireland
High-Pass Sigma-Delta Modulator
Van Tam Nguyen, Hervé Petit, Patrick Loumeau, Jean-François Naviner
Ecole Nationale Supérieure des Télécommunications de Paris - France
Mixed-Signal Clock-Skew Calibrator for Time-Interleaved Analog-to-Digital Converters
David Camarero, Karim Benkalaia, Jean-François Naviner, Patrick Loumeau
Ecole Nationale Supérieure des Télécommunications de Paris - France
Specification Validation of multistandard transceivers
Benjamin Nicolle, Alexandre Lewicki, William Tatinian, Gilles Jacquemod
University of Nice Sophia-Antipolis - France
Configuration Tool and FPGA-Prototype of a Hardware Packet Processing System
Stephan Kubisch, Harald Widiger, Peter Danielis, Dirk Timmermann, Christian Lange, Olivier Roewer, Daniel Duchow, Thomas Bahls
University of Rostock - Germany
Automatic Constraint Based Test Generation for Behavioral HDL Models
Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, V.M. Vedula, M. Kailashnath
University of Madras - India
Using Wireless Sensor Networks for an Interactive Musical Application
Jorge Portilla, Ana Belen Abril, Teresa Riesgo
University of Madrid - Spain
CAD tools dedicated to the design and test of RFICs
Yann Deval, Thierry Taris, Alexandre Shirakawa, Olivier Mazouffre, Vincent Pouget, Eric Kerhervé, Dean Lewis, Jean-Baptiste Bégueret
University of Bordeaux - France
Power Management & Estimation
SoftExplorer
Johann Laurent, Deepak Shankar
University of Bretagne Sud - France
Hyperion: A Sensor Node Test Bed for (High-Speed) Power Measurements
Dominic Hillenbrand, Michael Mende, Timothy Armstrong, Joerg Henkel
Univeristy of Karlsruhe - Germany
Wire Topology Optimization fot Low Power (TopCool and TopCool Viewer)
Paul Zuber, Robert Hartl, Thomas Ilnseher, Walter Stechele
University of Munich - Germany
The Power Analysis Tool for an Embedded Systems Development Board
Liang-Bi Chen, Tsung-Sheng Huang, Yueh-Ting Hsieh, Chien-Hung Chen, Yen-Ling Chen, Ing-Jer Huang
University of Kaohsiung - Taiwan - Republic of China
LEMOS Project: Low-Power Design Methods for Mobile Systems
Milan Schulte, Wolfgang Nebel, Ralf Pferdmenges
OFFIS Institure - Infineao Technologies - Germany
PowerComposer Demo: Software-level Power Estimation for TI C5510 DSPs
Chris Bleakley, Jose Rizo-Morente, Miguel Casas-Sanchez
University College Dublin - Ireland
DFM + Test & Yield Solutions
False Path Search Tool Kit
Fan Zhang
University of Bremen - Germany
IdEM & MpiLOG: Macromodeling Tools for System-Level Signal Integrity and EMC Assessment
M. Bandinu, F. Canavero, S. Grivet-Talocia, I. S. Stievano
Politecnico di Torino - Italy
Monte Carlo Simulation with Novel Statistical Design Kit
Wolfgang Schneider, Dirk Eichel, Michael Schröter, Holger Wittkopf
Atmel GmbH - University of Dresden - Germany
XSIM: An Efficient Simulator for Crosstalk Analysis between On-chip Interconnects
Kishore K. Duganapalli, Ajoy K. Palit, Walter Anheier
University of Bremen - Germany
SiSMA: Simulator for Statistical Mismatch Analysis
Giorgio Biagetti, Simone Orcioni, Alessandro Curzi, Paolo Crippa, Claudio Turchetti
University of Ancona - Italy
DefSim: the defective IC
Witold Pleskacz, Artur Jutman, Raimund Ubar, Sergei Devadze
University of Tallinn - Estonia
A 3D Timing Driven Placement Tool Considering Placement and Timing of Interchip Vias
Ole Ohlendorf, Markus Olbrich, Erich Barke
University of Hannover - Germany