GLSVLSI 2002 TABLE OF CONTENTS

Welcome
Symposium Organization
Reviewers

(F) Full Paper
(S) Short Paper

Keynote Address

A VLSI System Perspective for Microprocessors Beyond 100 nm

Shekhar Borkar (Circuits Research Lab, Intel Corp.)

Session 1: Low Power Design

(F) Power and CAD Considerations for the 1.75MByte, 1.2Ghz L2 Cache on the Alpha 21364 CPU [p. 1]

J. Grodstein (Compaq Computer, US), R. Rayess (Intel Corporation, USA), T. Truex, L. Shattuck (Compaq Computer, USA), S. Lowell, D. Bailey (Intel Corporation, USA), D. Bertucci (Compaq Computer, USA), G. Bischoff (Intel Corporation, USA), D. Dever (Compaq Computer, USA), M. Gowan (Intel Corporation, USA), R. Lane, B. Lilly (Compaq Computer, USA), K. Nagalla, R. Shah, E. Shriver (Intel Corporation, USA), S.-H. Yin, S. Morton (Compaq Computer, USA)

(F) Multi-Voltage Low Power Convolvers Using the Polynomial Residue Number System [p. 7]

V. Paliouras (University of Patras, Greece), A. Skavantzos (Louisiana State University, USA), T. Stouraitis (University of Patras, Greece)

(F) Properties of On-chip Inductive Current Loops [p. 12]

Andrey V. Mezhiba, Eby G. Friedman (University of Rochester, USA)

(S) Enhanced Clustered Voltage Scaling for Low Power [p. 18]

Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino (Politecnico Di Torino, Italy)

Session 2: Energy and Delay Considerations

(F) Unified Architecture Level Energy-Efficiency Metric [p. 24]

Victor Zyuban (T.J. Watson Research Center, USA)

(F) Fast and Accurate Wire Delay Estimation for Physical Synthesis of Large ASICs [p. 30]

Ruchir Puri, David S. Kung (IBM Thomas J. Watson Research Center, USA), Anthony D. Drumm (IBM Corporation, USA)

(F) A Compact Delay Model for Series-Connected MOSFETs [p. 37]

Kaveh Shakeri, James D. Meindl (Georgia Institute of Technology, USA)

(S) A Decoupling Method for Analysis of Coupled RLC Interconnects [p. 41]

Jun Chen, Lei He (University of Wisconsin, Madison, USA)

(S) Low Swing Dual Threshold Voltage Domino Logic [p. 47]

Volkan Kursun, Eby G. Friedman (University of Rochester, USA)

Session 3: Testing and Fault-Tolerance

(F) An Error Simulation Based Approach to Measure Error Coverage of Formal Properties [p. 53]

P. Azzoni (Strada le Grazie, 15, Italy), A. Fedeli (STMicroelectronics, Italy), F. Fummi (Strada le Grazie, 15, Italy), G. Pravadelli (Strada le Grazie, 15, Italy), U. Rossi, F. Toto (STMicroelectronics, Italy)

(F) Protected IP-Core Test Generation [p. 59]

Alessandro Fin, Franco Fummi (Strada le Grazie, 15, Italy)

(F) Test Generation for Resistive Opens in CMOS [p. 65]

Arun Krishnamachary, Jacob. A. Abraham (The University of Texas at Austin, USA)

(S) Self-Checking Sequential Circuits with Self-Healing Ability [p. 71]

Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin (Tel-Aviv University, Israel), Mark Karpovsky (Boston University, USA)

(S) Minimizing Concurrent Test Time in SoC's by Balancing Resource Usage [p. 77]

Dan Zhao, Shambhu Upadhyaya (SUNY at Buffalo, USA), M. Margala (University of Rochester, USA)

Session 4: VLSI Design

(F) Efficient Implementation of a Complex +/- 1 Multiplier [p. 83]

Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum (University of Rochester, USA)

(F) On the High-Speed VLSI Implementation of Errors-and-Erasures Correcting Reed-Solomon Decoders [p. 89]

Tong Zhang, Keshab K. Parhi (University of Minnesota, USA)

(F) Design Limitations in Deep Sub-0.1um CMOS SRAM [p. 94]

Robert K. Grube, Qi Wang, Sung-Mo Kang (University of California, Santa Cruz, USA)

(S) Reconfigurable Repetitive Padding Unit [p. 98]

Georgi Kuzmanov, Stamatis Vassiliadis (Delft University of Technology, The Netherlands)

Session 5: VLSI Circuits

(F) Energy-Delay Efficiency of VLSI Computations [p. 104]

Paul I. Pénzes, Alain J. Martin (California Institute of Technology, Pasadena, USA)

(F) Active Shields: A New Approach to Shielding Global Wires [p. 112]

Himanshu Kaul, Dennis Sylvester, David Blaauw (University of Michigan, Ann Arbor, USA)

(F) Variable-Segment and Variable-Driver Parallel Regeneration Techniques for RLC VLSI Interconnects [p. 118]

Falah R. Awwad, Mohamed Nekili (Concordia University, Montréal, Canada)

(S) Selective-Run Built-In Self-Test Using an Embedded Processor [p. 124]

Sungbae Hwang, Jacob A. Abraham (The University of Texas at Austin, USA)

Session 6: Design Automation

(F) Board-Level Multiterminal Net Assignment [p. 130]

Xiaoyu Song (Portland State University), William N. N. Hung (Intel Corporation, USA), Alan Mishchenko, Malgorzata Chrzanowska-Jeske (Portland State University), Alan Coppola (Cypress Semiconductor, USA), Andrew Kennings (University of Waterloo, Canada)

(F) Minimizing Resources in a Repeating Schedule for a Split-Node Data-Flow Graph [p. 136]

Timothy W. O'Neil, Edwin H.-M. Sha (University of Texas at Dallas, USA)

(F) A New Look at Hardware Maze Routing [p. 142]

John A. Nestor (Lafayette College, USA)

(S) Novel Interconnect Modeling by Using High-Order Compact Finite Difference Methods [p. 148]

Qinwei Xu, Pinaki Mazumder (University of Michigan, Ann Arbor, USA)

(S) AQUASUN: Adaptive Window Query Processing in CAD Applications for Physical Design and Verification [p. 153]

Michiel De Wilde, Dirk Stroobandt, J. Van Campenhout, Peter Verplaetse (Ghent University, Belgium)

Session 7: Potpourri

(F) Term Ordering Problem on MDG [p. 160]

Yi Feng, Eduard Cerny (Université de Montréal, Canada)

(S) A Low Power Direct Digital Frequency Synthesizer with 60 dBc Spectral Purity [p. 166]

J.M.P. Langlois, Dhamin Al-Khalili (Royal Military College of Canada, Canada)

(S) Novel Design and Verification of a 16 x 16-b Self-Repairable Reconfigurable Inner Product Processor [p. 172]

Rong Lin (SUNY-Geneseo, USA), Martin Margala (University of Rochester, USA)

(S) Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations [p. 178]

W.J. Townsend, M. A. Thornton (Mississippi State University), R. Drechsler (University of Bremen, Germany), D. M. Miller (University of Victoria, Canada)