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Reconfigurable Architectures Workshop - RAW
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Workshop Introduction - RAW
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A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Christopher Claus, Florian H. Mueller, Johannes Zeppenfeld and Walter Stechele
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Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
Vincenzo Rana, Marco Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Koester, Mario Porrmann and Ulrich Rueckert
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Communication Architectures for Dynamically Reconfigurable FPGA Designs
Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner and Jürgen Becker
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Optimization of Area and Performance by Processor-Like Reconfiguration
Tobias Oppold, Sven Eisenhardt and Wolfgang Rosenstiel
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Splice: A Standardized Peripheral Logic and Interface Creation Engine
Justin Thiel and Ron K. Cytron
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Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms
Maurizio Palesi, Shashi Kumar, Rickard Holsmark and Vincenzo Catania
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Power-Aware Routing for Well-Nested Communications On The Circuit Switched Tree
Hatem M. El-boghdadi
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Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
Carlos Morra, Joao M. P. Cardoso and Juergen Becker
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Interconnect Customization for a Coarse-grained Reconfigurable Fabric
Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker and Alex K. Jones
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A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template
Akira Hatanaka and Nader Bagherzadeh
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A CAM Emulator Using Look-Up Table Cascades
Hiroki Nakahara, Tsutomu Sasao and Munehiro Matsuura
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A Reconfigurable Computing Engine for Wavelet Transforms
Kang Sun, Xuezeng Pan and Lingdi Ping
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Using an FPGA for Fast Bit Accurate SoC Simulation
Pascal T. Wolkotte, Philip K. F. Hölzenspies and Gerard J. M. Smit
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A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
Alisson V. Brito, Matthias Kuehnle, Elmar U. K. Melcher and Juergen Becker
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CONFETTI : A reconfigurable hardware platform for prototyping cellular architectures
Pierre- André Mudry, Fabien Vannel, Gianluca Tempesti and Daniel Mange
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A Reconfigurable Load Balancing Architecture for Molecular Dynamics
Jonathan Phillips, Matthew Areno, Chris Rogers, Aravind Dasu and Brandon Eames
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Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides and Dhiraj K. Pradhan
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Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications
Sajid Baloch, Tughrul Arsaln and Adrian Stoica
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A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA
Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert and Fernando Moraes
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Hierarchical Cluster Assignment for Coarse-Grain Reconfigurable Coprocessors
Martino Sykora, Davide Pavoni, Joel Cambonie, Roberto Costa and Stefano Crespi Reghizzi
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QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks
Sunil Shukla, Neil W. Bergmann and Jürgen Becker
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Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path
Michalis D. Galanis, Gregory Dimitroulakos and Costas E. Goutis
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Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor
Ying Chen and Simon Y. Chen
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A Reconfiguration Aware Circuit Mapper for FPGAs
Markus Rullmann and Renate Merker
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Miss Ratio Improvement For Real-Time Applications Using Fragmentation-Aware Placement
Ahmed Abou Elfarag, Hatem M. El-boghdadi and Samir I. Shaheen
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Managing dynamic reconfiguration on MIMO Decoder
Hongzhi Wang, Jean-philippe Delahaye, Pierre Leray and Jacques Palicot
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Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems
Florian Dittmann, Marcelo Götz and Achim Rettberg
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An Architectural Framework for Automated Streaming Kernel Selection
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer and Dan Linzmeier
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High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs
Maik Boden, Thomas Fiebig, Torsten Meissner, Steffen Ruelke and Juergen Becker
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A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays
Rio Miyazaki, Minoru Watanabe and Fuminori Kobayashi
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Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan and Ahmet Erdogan
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C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Mattias O'nils, Benny Thornberg and Najeem Lawal
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A Study of Design Efficiency with a High-Level Language for FPGAs
Zain-ul-abdin and Bertil Svensson
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