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The 12th Asia and South Pacific Design Automation Conference

Session 1D University Design Contest
Time: 10:15 - 12:20 Wednesday, January 24, 2007
Location: Room 416+417
Chairs: Makoto Nagata (Kobe Univ., Japan), Fumio Arakawa (Hitachi, Japan)

1D-1 (Time: 10:15 - 10:20)
TitleA 1Tb/s 3W Inductive-Coupling Transceiver Chip
Author*Noriyuki Miura, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 92 - 93
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1D-2 (Time: 10:20 - 10:25)
Title22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors
Author*Ahmet Oncu, B.B.M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima (Univ. of Tokyo, Japan)
Pagepp. 94 - 95
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1D-3 (Time: 10:25 - 10:30)
TitleA 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18µm CMOS
Author*Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi (Gunma Univ., Japan), Masao Hotta (Musashi Inst. of Tech., Japan)
Pagepp. 96 - 97
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1D-4 (Time: 10:30 - 10:35)
TitleA Wideband CMOS LC-VCO Using Variable Inductor
Author*Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Pagepp. 98 - 99
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1D-5 (Time: 10:35 - 10:40)
TitleDesign of Active Substrate Noise Canceller using Power Suplly di/dt Detector
Author*Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo, Japan)
Pagepp. 100 - 101
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1D-6 (Time: 10:40 - 10:45)
TitleA 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
Author*Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu (Inst. of Communications Engineering, NTHU, Taiwan), Shuo-Hung Hsu (Inst. of Electronics Engineering, NTHU, Taiwan)
Pagepp. 102 - 103
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1D-7 (Time: 10:45 - 10:50)
TitleReconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation
Author*Satoshi Fukuda, Daisuke Kawazoe, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Pagepp. 104 - 105
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1D-8 (Time: 10:50 - 10:55)
TitlePseudo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems
Author*Chee Hong Ivan Lai, Minoru Fujishima (Univ. of Tokyo, Japan)
Pagepp. 106 - 107
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1D-9 (Time: 10:55 - 11:00)
TitleImproving Execution Speed of FPGA using Dynamically Reconfigurable Technique
AuthorRoel Pantonial, Md. Ashfaquzzaman Khan, *Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ., Japan)
Pagepp. 108 - 109
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1D-10 (Time: 11:00 - 11:05)
TitleSingle-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
Author*Li-Chun Lin, Shih-Hao Ou (National Chiao Tung Univ., Taiwan), Tay-Jyi Lin (Industrial Technology Research Institute, Taiwan), Siang-Sen Deng, Chih-Wei Liu (National Chiao Tung Univ., Taiwan)
Pagepp. 110 - 111
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1D-11 (Time: 11:05 - 11:10)
TitleA Highly Integrated 8 mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16 MHz SoC Platform
AuthorHuan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, *Wei-Cheng Hung, Kai-Yuan Jan (National Tsing Hua Univ., Taiwan)
Pagepp. 112 - 113
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1D-12 (Time: 11:10 - 11:15)
TitleConfigurable AMBA On-Chip Real-Time Signal Tracer
Author*Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 114 - 115
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1D-13 (Time: 11:15 - 11:20)
TitleImplementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
Author*Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ., Japan), Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu (ROHM, Japan)
Pagepp. 116 - 117
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1D-14 (Time: 11:20 - 11:25)
TitleA Multi-Drop Transmission-Line Interconnect in Si LSI
Author*Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Pagepp. 118 - 119
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1D-15 (Time: 11:25 - 11:30)
TitleA 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology
Author*Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 120 - 121
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1D-16 (Time: 11:30 - 11:35)
TitleA 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations
Author*Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 122 - 123
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1D-17 (Time: 11:35 - 11:40)
TitleA 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
Author*Minoru Watanabe, Fuminori Kobayashi (Kyushu Inst. of Tech., Japan)
Pagepp. 124 - 125
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1D-18 (Time: 11:40 - 11:45)
TitleLow-Power High-Speed 180-nm CMOS Clock Drivers
Author*Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi (Chuo Univ., Japan)
Pagepp. 126 - 127
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