ISPD 2002 AUTHOR INDEX

[A] [B] [C] [D] [G] [H] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [W] [X] [Y] [Z]

A

Adya, S.N.
Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement [p. 12]
Alpert, C.J.
Buffer Insertion with Adaptive Blockage Avoidance [p. 92]
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]

B

Brenner, U.
An Effective Congestion Driven Placement Framework [p. 6]

C

Chang, C.-C.
Physical Hierarchy Generation with Routing Congestion Control [p. 36]
Chang, H.-L.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]
Chen, C.
Physical Design with Multiple On-Chip Voltages [p. 118]
Chen, L.H.
Incremental Delay Change Due to Crosstalk Noise [p. 120]
Chen, P.
On Convergence of Switching Windows Computation in Presence of Crosstalk Noise [p. 84]
Chen, Y.
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis [p. 137]
Cheon, Y.
Design Hierarchy Guided Multilevel Circuit Partitioning [p. 30]
Choi, B.-K.
Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement [p. 42]
Chrzanowska-Jeske, M.
Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs [p. 56]
Chu, C.-N.
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]
Twin Binary Sequences: A Non-Redundant Representation for General Non-slicing Floorplan [p. 196]
Cong, J.
Physical Hierarchy Generation with Routing Congestion Control [p. 36]
Global Clustering-Based Performance-Driven Circuit Partitioning [p. 149]
Timing Closure Based on Physical Hierarchy [p. 170]

D

Dai, W.W.-M.
TEG: A New Post-Layout Optimization Method [p. 62]
Daniel, L.
Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis [p. 202]
De, V.
Leakage-Tolerant Design Techniques for High Performance Processors [p. 28]

G

Gandham, G.
Buffer Insertion with Adaptive Blockage Avoidance [p. 92]
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]
Gupta, S.
Shield Count Minimization in Congested Regions [p. 78]

H

Hashimoto, M.
Crosstalk Noise Optimization by Post-Layout Transistor Sizing [p. 126]
Hrkic, M.
Buffer Tree Synthesis with Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost and Blockages [p. 98]
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]
Hu, B.
FAR: Fixed-Points Addition and Relaxation Based Placement [p. 161]
Hu, J.
Buffer Insertion with Adaptive Blockage Avoidance [p. 92]
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]

K

Kahng, A.B.
A Roadmap and Vision for Physical Design [p. 112]
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis [p. 137]
Min-Max Placement For Large Scale Timing Optimization [p. 143]
Kang, S.-M.
On-chip Thermal Engineering for Peta-scale Integration [p. 76]
Kashyap, C.
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]
Keutzer, K.
On Convergence of Switching Windows Computation in Presence of Crosstalk Noise [p. 84]
Kukimoto, Y.
On Convergence of Switching Windows Computation in Presence of Crosstalk Noise [p. 84]

L

Lee, K.H.
Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis [p. 202]
Lee, S.
Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation [p. 176]
Lillis, J.
Buffer Tree Synthesis with Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost and Blockages [p. 98]
Liu, J.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]
Low, S.C.
Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis [p. 202]
Lu, B.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]

M

Mak, W.-K.
Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning [p. 190]
Mantik, S.
Min-Max Placement For Large Scale Timing Optimization [p. 143]
Marek-Sadowska, M.
Incremental Delay Change Due to Crosstalk Noise [p. 120]
FAR: Fixed-Points Addition and Relaxation Based Placement [p. 161]
Markov, I.L.
Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement [p. 12]
Min-Max Placement For Large Scale Timing Optimization [p. 143]

N

Nassif, S.R.
An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts [p. 68]

O

Ong, C.S.
Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis [p. 202]
Onodera, H.
Crosstalk Noise Optimization by Post-Layout Transistor Sizing [p. 126]

P

Pan, Z.
Physical Hierarchy Generation with Routing Congestion Control [p. 36]
Pandini, D.
Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping [p. 131]
Pileggi, L.T.
Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping [p. 131]

Q

Quay, S.T.
Buffer Insertion with Adaptive Blockage Avoidance [p. 92]
Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique [p. 104]

R

Rafiq, F.
Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs [p. 56]
Robins, G.
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis [p. 137]
Rohe, A.
An Effective Congestion Driven Placement Framework [p. 6]
Rutenbar, R.A.
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing [p. 182]

S

Sakallah, K.
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing [p. 182]
Sapatnekar, S.S.
An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts [p. 68]
Sarrafzadeh, M.
Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement [p. 42]
Saxena, P.
Shield Count Minimization in Congested Regions [p. 78]
Sham, C.W.
Routability Driven Floorplanner with Buffer Block Planning [p. 50]
Shen, Z.C.
Twin Binary Sequences: A Non-Redundant Representation for General Non-slicing Floorplan [p. 196]
Sherwani, N.
Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs [p. 56]
Shragowitz, E.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]
Strojwas, A.J.
Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping [p. 131]
Su, H.
An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts [p. 68]
Sutanthavibul, S.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]

T

Takahashi, M.
Crosstalk Noise Optimization by Post-Layout Transistor Sizing [p. 126]
Teig, S.T.
Challenges and Principles of Physical Design [p. 3]
Teng, C.-C.
On Convergence of Switching Windows Computation in Presence of Crosstalk Noise [p. 84]

W

White, J.
Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis [p. 202]
Wong, D.F.
Design Hierarchy Guided Multilevel Circuit Partitioning [p. 30]
Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation [p. 176]
Wu, C.
Global Clustering-Based Performance-Driven Circuit Partitioning [p. 149]

X

Xu, H.
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing [p. 182]

Y

Yang, H.H.
Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs [p. 56]
Yang, X.
Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement [p. 42]
Yeap, G.C.-F.
Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges [p. 22]
Young, E.F.Y.
Routability Driven Floorplanner with Buffer Block Planning [p. 50]
Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning [p. 190]
Twin Binary Sequences: A Non-Redundant Representation for General Non-slicing Floorplan [p. 196]
Youseff, H.
Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design [p. 155]
Yuan, X.
Physical Hierarchy Generation with Routing Congestion Control [p. 36]

Z

Zelikovsky, A.
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis [p. 137]
Zhang, S.
TEG: A New Post-Layout Optimization Method [p. 62]