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36th
Annual International Symposium on Microarchitecture |
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Sponsored by IEEE TC-MARCH
and ACM
SIGMICRO 
Micro 36 Program on CD
Important Notes:
- All papers are copyright of the IEEE, Inc.
- The symposium CD-ROM is published by the Micro-36 organizing committee; the symposium proceedings is published by the IEEE Computer Society.
- All papers are available in portable document (pdf) format. Acrobat reader can be downloaded:
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Download Adobe Acrobat Reader |
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Sessions
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Session
8: Dataflow, Data Parallel, and Clustered Architectures |
Keynote Speak 1
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Microarchitecture
on the MOSFET Diet Kerry Bernstein IBM T. J. Watson Research Center |
Session 1: Voltage Scaling &
Transient Faults
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Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation Dan Ernst, Nam Sung Kim, Sanjay Pant, Shidhartha Das, Rajeev Rao, Toan
Pham, Conrad Ziesler, David Blaauw, Todd Austin, University of Michigan;
Krisztian Flautner, ARM Ltd.; Trevor Mudge, University of Michigan. VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy, Purdue. Shubhendu S. Mukherjee, Christopher T. Weaver, Joel Emer, Intel
Corporation; Steven K. Reinhardt, Intel Corporation and University
of Michigan; Todd Austin, University of Michigan. |
Session 2: Cache Design
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Bradford M. Beckmann, David A. Wood, University of
Wisconsin-Madison. Distance Associativity for High-Performance Energy-Efficient, Non-Uniform
Cache Architectures Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar, Purdue. Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches Se-Hyun Yang, Babak Falsafi, Carnegie Mellon University. |
Session 3: Power and Energy
Efficient Architectures
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Single-ISA Heterogeneous Multi-Core Architectures: The Potential for
Processor Power Reduction Rakesh Kumar, UCSD; Keith Farkas, Norman Jouppi, Partha
Ranganathan, HP Labs; Dean Tullsen, UCSD. Run-time Power Monitoring in High-End Processors: Methodology and
Empirical Data Canturk Isci, Margaret Martonosi, Princeton University. Power-driven Design of Router Microarchitectures in On-chip Networks Hangsheng Wang, Li-Shiuan Peh, Sharad Malik, Department of
Electrical Engineering - Princeton University. Optimum Power/Performance Pipeline Depth Allan Hartstein, Thomas R. Puzak, IBM T. J. Watson Research Center. |
Session 4: Application-Specific
Optimization and Analysis
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Processor Acceleration through Automated Instruction Set
Customization Nathan Clark, Hongtao Zhong, Scott Mahlke, University of Michigan. The Reconfigurable Streaming Vector Processor (RSVPä) Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim
Norris, Michael Schuette, Motorola Labs; Ali Saidi, The Mitre
Corporation. Scaling and Characterizing Database Workloads: Bridging the Gap between
Research and Practice Richard Hankins, Trung Diep, Murali Annavaram, Intel; Brian
Hirano, Harald Eri, Oracle; Hubert Nueckel, John Shen, Intel. |
Keynote Speak 2
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Micheal Schlansker Hewlett-Packard Laboratories |
Session 5: Dynamic Optimization
Systems
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Generational Cache Management of Code Traces in Dynamic Optimization
Systems Kim Hazelwood, Michael D. Smith, Harvard University. The Performance of Runtime Data Cache Prefetching in a Dynamic
Optimization System Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung
Yew, Univ. of Minnesota - Twin Cities; Dong-Yuan Chen, Intel. IA-32 Execution Layer: a two phase dynamic translator designed to
support IA-32 applications on Itaniumâ-based systems Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex
Skaletsky, Yun Wang, Yigal Zemach, Intel. |
Session 6: Dynamic Program Analysis
and Optimization
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LLVA: A Low-level Virtual Instruction Set Architecture Vikram Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian
Gaeke, University of Illinois at Urbana-Champaign. Comparing Program Phase Detection Techniques Ashutosh S. Dhodapkar, James E. Smith, University of
Wisconsin-Madison. Using Interaction Costs for Microarchitectural Bottleneck Analysis Brian A. Fields, Rastislav Bodik, University of
California-Berkeley; Mark D. Hill, University of Wisconsin-Madison;
Chris J. Newburn, Intel. |
Session 7: Branch, Value, and
Scheduling Optimizations
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Fast Path-Based Neural Branch Prediction Daniel A. Jiménez, Rutgers University. Hardware Support for Control Transfers in Code Caches Ho-Seop Kim, James E. Smith, University of Wisconsin-Madison. Exploiting Value Locality in Physical Register Files Saisanthosh Balakrishnan, Gurindar S. Sohi, University of
Wisconsin-Madison. Macro-op Scheduling: Relaxing Scheduling Loop Constraints Ilhyun Kim, Mikko H. Lipasti, University of Wisconsin-Madison. |
Session 8: Dataflow, Data Parallel, and Clustered Architectures
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Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin, University of Washington. Universal Mechanisms for Data Parallel Architectures Karthikeyan
Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger, University
of Texas - Austin. Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors Enric Gibert, UPC - Barcelona; Jesús Sánchez, Antonio González, UPC - Barcelona and Intel Labs - Barcelona. Instruction Replication for Clustered Architectures Alex Aletŕ, Josep M.
Codina, UPC - Barcelona; Antonio González, UPC - Barcelona and Intel
Labs - Barcelona; David Kaeli, Northeastern University. |
Session 9: Secure and Network
Processors
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Efficient Memory Integrity Verification and Encryption for Secure
Processor G. Edward Suh, Dwaine Clarke, Blaise Gassend, MIT; Marten van
Dijk, Philips; Srinivas Devadas, MIT. Fast Secure Processor for Inhibiting Software Piracy and Tampering Jun Yang, University of California-Riverside;Youtao Zhang, University
of Texas-Dallas; Lan Gao, University of California-Riverside. IPStash: A Power-Efficient Memory Architecture for IP Lookup Stefanos Kaxiras, Agere Systems; Georgios Keramidas, Department
of ECE - Univ. of Patras. Design and Implementation of High-Performance Memory Systems for Future
Packet Buffers Jorge Garcia, Jesus Corbal, Llorenç Cerdŕ, Mateo Valero, UPC -
Barcelona. |
Session 10: Scaling Design
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Beating In-Order Stalls with "Flea-Flicker" Two-Pass
Pipelining Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel,
Nacho Navarro, Wen-mei W. Hwu, University of Illinois at Urbana-Champaign. Scalable Hardware Memory Disambiguation for High ILP Processors Simha Sethumadhavan, Department of Computer Sciences - UT Austin; Rajagopalan
Desikan, Department of Electrical and Computer Engineering - UT Austin; Doug
Burger, Charles R. Moore, Stephen W. Keckler, Department of Computer
Sciences - UT Austin. Reducing Design Complexity of the Load/Store Queue Il Park, Chong Liang Ooi, T. N. Vijaykumar, Purdue. Checkpoint Processing and Recovery: Towards Scalable Large Instruction
Window Processors Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Intel. |
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General
Chair |
Bill
Mangione-Smith |
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Program
Chair |
Brad
Calder |
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Local
Arrangements Chair |
Dean
Tullsen, UC San Diego |
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Workshop
and Tutorial Chair |
Glenn
Reinman, UCLA |
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Publicity
Chair |
Jason
Fritts, Washington U. |
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Publication
Chair |
Gokhan
Memik, Northwestern U. |
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Registration
Chair |
Roger
Bringmann, Agere Systems |
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Steering
Committee |
Richard
Belgard, Consultant, Chariman |
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Program
Committee |
Saman
Amarasinghe, MIT |