Table of Contents

Computer Architecture in the Many-Core Era.................................................................................................... 1

Scaling Manufacturability Software to Thousands of Processors....................................................................... 2

Chair: Tejas Karkhanis, AMD

Long-term Performance Bottleneck Analysis and Prediction............................................................................. 3

Dynamic Code Value Specialization Using the Trace Cache Fill Unit............................................................. 10

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address

Buses ................................................................................................................................................................ 17

Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing............... 25

A Low Power Highly Associative Cache for Embedded Systems.................................................................... 31

Chair: Florentin Dartu, Synopsys

On the Improvement of Statistical Timing Analysis......................................................................................... 37

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling................................. 43

Reduction of Crosstalk Pessimism using Tendency Graph Approach.............................................................. 50

Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations

with Spatial Correlation .................................................................................................................................... 56

Chair: Srinivas Raghvendra, Synopsys

RasP: An Area-efficient, On-chip Network ...................................................................................................... 63

Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire

Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects............................................................. 70

CMOS Comparators for High-Speed and Low-Power Applications................................................................ 76

A Reconfigurable CAM Architecture for Network Search Engines................................................................. 82

Delay and Area Efficient First-level Cache Soft Error Detection and Correction............................................ 88

Chair: Pranav Ashar, Real Intent Inc.

Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD............ 93

Chair: Suleyman Sair, North Carolina State University

Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy..................... 101

Customizable Fault Tolerant Caches for Embedded Processors.................................................................... 108

Reduce Register Files Leakage Through Discharging Cells........................................................................... 114

Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution................. 120

Chair: Huiyang Zhou, University of Central Florida

Dynamic Co-Processor Architecture for Software Acceleration on CSoCs ................................................... 127

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.................................................. 134

A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips............. 142

Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors................................................ 148

Chair: Larry Clark, Arizona State University

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals........ 155

Design Methodology of Regular Logic Bricks for Robust Integrated Circuits............................................... 162

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.... 168

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles ............................................... 174

Chair: Kee Sup Kim, Intel

Scale in Chip Interconnect requires Network Technology ............................................................................. 180

Interconnect Considerations For High Performance Network on Chip Designs............................................. 187

Addressing Multicore Communication Challenges Using NoC Technology ................................................. 188

Chair: Jiangjiang Liu, Lamar University

Clustering-Based Microcode Compression..................................................................................................... 189

Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling............. 197

An Enhancement for a Scheduling Logic Pipelined over two Cycles............................................................. 203

Chair: Azita Emami, Columbia University

Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates ................ 210

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI ........ 216

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.................. 222

Chair: Rob Aitken, ARM

Power-Constrained SOC Test Schedules through Utilization of Functional Buses........................................ 230

RTL Scan Design for Skewed-Load At-speed Test under Power Constraints................................................ 237

Power Droop Testing ...................................................................................................................................... 243

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation..................... 251

Chair: Carl Pixley, Synopsys

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations.................................. 259

Seqver : A Sequential Equivalence Verifier for Hardware Designs ............................................................... 267

High-Level vs. RTL Combinational Equivalence: An Introduction ............................................................... 274

Chair: Jason Baumgartner, IBM

Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique.................. 280

Requirements and Concepts for Transaction Level Assertions....................................................................... 286

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.............. 294

Simulation-based Functional Test Justification Using a Boolean Data Miner................................................ 300

Chair: Jamil Kawa, Synopsys

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method........................................... 308

FPGA-based Design of a Large Moduli Multiplier for Public-Key Cryptographic Systems ......................... 314

Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture .................................... 320

An Efficient, Scalable Hardware Engine for Boolean SATisfiability............................................................. 326

Chair: Saurabh Adya, Synplicity

Power/Ground Supply Network Optimization for Power-Gating................................................................... 332

A Pattern Generation Technique for Maximizing Power Supply Currents..................................................... 338

Partial Functional Manipulation Based Wirelength Minimization ................................................................. 344

Iterative-Constructive Standard Cell Placer for High Speed and Low Power ................................................ 350

Chair: Mauricio Breternitz Jr., Intel

Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific

Pipelined IPs.................................................................................................................................................... 356

Assertion-Based Microarchitecture Design for Improved Fault Tolerance .................................................... 362

High-Speed Factorization Architecture for Soft-Decision Reed-Solomon Decoding..................................... 370

Chair: Roozbeh Jafari, UC Berkeley

Guiding Architectural SRAM Models ............................................................................................................ 376

A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models.... 383

Reliability Support for On-Chip Memories Using Networks-on-Chip........................................................... 389

Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multiprocessor

Systems..................................................................................................................................................... 397

Chair: Dan Sorin, Duke University

A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems...................................... 405

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors.......................... 411

Improving Power and Data Efficiency with Threaded Memory Modules...................................................... 417

Chair: Yervant Zorian, Virage Logic Corp.

A New Class of Sequential Circuits with Acyclic Test Generation Complexity............................................ 425

Efficient Testing of RF MIMO Transceivers Used in WLAN Applications .................................................. 432

A Theory of Error-Rate Testing...................................................................................................................... 438

Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on

Stuck-at Tests.................................................................................................................................................. 446

Chair: Anup Hosangadi, Cadence

Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach................................... 452

Design and Implementation of Software Objects in Hardware....................................................................... 458

An Accurate Energy Estimation Framework for VLIW Processor Cores ...................................................... 464

Chair: Steve Keckler, University of Texas at Austin

Design and Implementation of the TRIPS Primary Memory System............................................................. 470

Implementation and Evaluation of On-Chip Network Architectures.............................................................. 477

Microarchitecture and Performance Analysis of Godson-2 SMT Processor .................................................. 485

Patching Processor Design Errors................................................................................................................... 491

Chair: Eric Rotenberg, NC State University

Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache............................................... 499

Architectural Support for Run-Time Validation of Control Flow Transfer.................................................... 506

Pesticide: Using SMT Processors to Improve Performance of Pointer-Bug Detection .................................. 514

Chair: Pranav Ashar, Real Intent Inc.

Trends and Future Directions in Nano Structure Based Computing and Fabrication..................................... 522