|
|
20th IEEE International Parallel & Distributed
Processing Symposium
April 25-29, 2006
Rhodes Island, Greece
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Technical Committee on
Parallel Processing |
|
|
|
|
|
|
|
|
|
|
|
Session 23: Reconfigurable and Multiple-Width Systems
|
|
|
|
Parallel FPGA-based All-Pairs Shortest-Paths in a Directed Graph
Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan
|
|
Design flow for Optimizing Performance in Processor Systems with on-chip Coarse-Grain Reconfigurable Logic
Michalis D. Galanis, Gregory Dimitoulakos, Costas E. Goutis
|
|
Exploring the Design Space of an Optimized Compiler Approach for Mesh-Like Coarse-Grained Reconfigurable Architectures
Gregory Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
|
|
Empowering a Helper Cluster through Data-Width Aware Instruction Selection Policies
Osman S. Unsal, Xavier Vera, Antonio González, Oguz Ergin
|
|
|
|
|
|
|
|
|
