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The 12th Asia and South Pacific Design Automation Conference

Session 7B Uncertainty Aware Interconnect Design
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 413
Chairs: Chih-Tsun Huang (National Tsing Hua Univ., Taiwan), Takashi Sato (Tokyo Inst. of Tech., Japan)

7B-1 (Time: 10:15 - 10:40)
TitleApproaching Speed-of-light Distortionless Communication for On-chip Interconnect
AuthorHaikun Zhu, Rui Shi (Univ. of California, San Diego, United States), Hongyu Chen (Synopsys Inc., United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States)
Pagepp. 684 - 689
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7B-2 (Time: 10:40 - 11:05)
TitleDelay Uncertainty Reduction by Interconnect and Gate Splitting
AuthorVineet Agarwal, Jin Sun, Alexandar Mitev, *Janet Wang (Univ. of Arizona, Tucson, United States)
Pagepp. 690 - 695
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7B-3 (Time: 11:05 - 11:30)
TitleTransition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects
Author*Charbel Akl, Magdy Bayoumi (Univ. of Louisiana, Lafayette, United States)
Pagepp. 696 - 701
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7B-4 (Time: 11:30 - 11:55)
TitleFast Buffered Delay Estimation Considering Process Variations
AuthorTien-Ting Fang, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 702 - 707
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7B-5 (Time: 11:55 - 12:20)
TitlePredicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Author*Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud (Rice Univ., United States)
Pagepp. 708 - 713
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