| Title | Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits |
| Author | Youngsoo Shin, Sewan Heo, *Hyung-Ock Kim (KAIST, Republic of Korea), Jung Yun Choi (Samsung Electronics, Republic of Korea) |
| Page | pp. 654 - 659 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Runtime Leakage Power Estimation Technique for Combinational Circuits |
| Author | *Yu-Shiang Lin, Dennis Sylvester (Univ. of Michigan, United States) |
| Page | pp. 660 - 665 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Logic and Layout Aware Voltage Island Generation for Low Power Design |
| Author | *Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China) |
| Page | pp. 666 - 671 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost |
| Author | Tsung-Yi Wu, Jr-Luen Tzeng, *Kuang-Yao Chen (National Changhua Univ. of Education, Taiwan) |
| Page | pp. 672 - 677 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs |
| Author | *Hassan Hassan, Mohab Anis, Mohamed Elmasry (Univ. of Waterloo, Canada) |
| Page | pp. 678 - 683 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |