| Title | Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits |
| Author | Youngsoo Shin, Sewan Heo, *Hyung-Ock Kim (KAIST, Republic of Korea), Jung Yun Choi (Samsung Electronics, Republic of Korea) |
| Page | pp. 654 - 659 |
| Keyword | low power, leakage, power gating, design methodology, gate leakage |
| Abstract | Power gating has been widely used to reduce subthreshold leakage.
However, its efficiency degrades very fast with technology scaling
due to the gate leakage of circuits specific to power gating,
such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65nm and 8.6 with 45nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from RTL to layout. The proposed design flow is demonstrated on a commercial design with 90nm
technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively. |
| PDF file |
| Title | Logic and Layout Aware Voltage Island Generation for Low Power Design |
| Author | *Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China) |
| Page | pp. 666 - 671 |
| Keyword | Voltage Island, Low Power, Placement, Level Converter |
| Abstract | Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but all of them do not consider level converters which have an important effect in dual-vdd design. In this work we propose a logic and layout aware approach for voltage assignment and voltage island generation in placement process to minimize the number of level converters and to implement voltage islands with minimal overheads. Experimental results show that our approach uses much less level converters than the approach in [1] (reduced by 59.50% on average) when achieving the same power savings. The approach is able to produce feasible placement with a small impact
to traditional placement goals. |
| PDF file |
| Title | A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost |
| Author | Tsung-Yi Wu, Jr-Luen Tzeng, *Kuang-Yao Chen (National Changhua University of Education, Taiwan) |
| Page | pp. 672 - 677 |
| Keyword | Minimum Leakage Vector, Input Vector Control, Leakage Current Reduction, Sleep Mode, Low Power Design |
| Abstract | In this paper, we propose a probability-based algorithm that can rapidly find a minimum leakage vector (MLV). Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can consider it. Ignoring this overhead during solution exploration brings a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 85% of MCNC benchmarks. |
| PDF file |