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The 11th Asia and South Pacific Design Automation Conference

Thursday January 26, 2006

Session 4A Resolving Timing Issues: Design and Test (10:15 - 12:20)
Location: Room 411+412
Chair(s): Masaki Hashizume (Tokushima Univ., Japan), Kazumi Hatayama (Renesas, Japan)

4A-1 (Time: 10:15 - 10:40)
TitleDelay Defect Screening for a 2.16GHz SPARC64 Microprocessor
AuthorNoriyuki Ito, *Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi (Fujitsu, Japan)
Pagepp. 342 - 347
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4A-2 (Time: 10:40 - 11:05)
TitleA Dynamic Test Compaction Procedure for High-quality Path Delay Testing
AuthorMasayasu Fukunaga (Fujitsu, Japan), Seiji Kajihara, *Xiaoqing Wen (Kyushu Inst. of Tech., Japan), Toshiyuki Maeda, Shuji Hamada, Yasuo Sato (STARC, Japan)
Pagepp. 348 - 353
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4A-3 (Time: 11:05 - 11:30)
TitleDelay Variation Tolerance for Domino Circuits
AuthorKai-Chiang Wu, *Cheng-Tao Hsieh, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Pagepp. 354 - 359
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4A-4 (Time: 11:30 - 11:55)
TitleEfficient Identification of Multi-Cycle False Path
AuthorKai Yang, *Tim Cheng (Univ. of California, Santa Barbara, United States)
Pagepp. 360 - 365
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4A-5 (Time: 11:55 - 12:20)
TitleIEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
Author*Katherine Shu-Min Li (National Chiao Tung Univ., Taiwan), Yao-Wen Chang (National Taiwan Univ., Taiwan), Chauchin Su, Chung-Len Lee (National Chiao Tung Univ., Taiwan), Jwu E Chen (National Central Univ., Taiwan)
Pagepp. 366 - 371
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