- 1.
- Required Material:
All students should have access to ICS151/ICS152 textbook "Principles of Digital
Design" for refreshing their memory.
- 2.
- Course Objective:
The objective of this course is to learn how to specify, model, optimize,
design and test hardware executing a given software. For the modeling we
will be using the hardware description language VHDL and corresponding
commercial simulators and other CAD tools. Given models on three
different levels of abstraction, students will be asked to enhance these
models by optimizing the hardare/software design.
Finally, the models are analyzed by executing certain benchmarks in order
to ensure satisfaction of performance constraints.
- 3.
- Tentative Lab Outlines:
The lab portion of this course consists of 5 assignments. Each
assignment involves the design, modeling and simulation of a module or
feature of the digital processor or the ASIC.
Lab 1 requires to execute the given C program in order to extract test vectors and input patterns which will then be used to debug the behavioral VHDL model given in class. Students will compose C and VHDL code and make sure that both descriptions execute the same functionality.
In Lab 2 the FSMD model of computation will be introduced into the design. We will be developing the FSMD model for the program given in Lab 1. In addition, students are required to optimize the design for performance by applying loop unrolling, chaining and multicycling techniques. Finally, the model has to be tested and simulated in order to prove equivalence with the model of Lab 1.
Lab 3 requires students to introduce multithreading and pipelining techniques into the model obtained in Lab 2. The model is tested to prove equivalence with the model in Lab 2.
Lab 4 is targeted towards development of a structural register-transfer model in which the original C program is modeled as a control unit plus datapath. Furthermore, the control unit is modeled as an FSM and the datapath as a netlist consisting of storage elements and functional units.
Lab 5 is the final assignment in which students combine all the design techniques learned so far in order to explore performance/cost tradeoffs and generate the most optimal design under the given constraints. The result is modeled and tested on the register-transfer level described in Lab 4.
The lab format may change a little through the quarter. However, you should plan or spending approximately 10 hours a week in the lab. You can often reduce the time spent in the lab by doing your designs before coming to the lab. If the lab gets crowded and students have trouble accessing the machines, we will use sign-up sheets for scheduling use of the lab.
- 4.
- Course Schedule:
During the class lectures, we will discuss principles of modeling,
software/hardware optimization and implementation, and how these issues
are related to the lab assignments.
The lectures serve primarily as a guide to the labs. Their primary objective is to discuss lab assignment and to review material. All announcements will be made at the beginning of the class. It is your responsibility to come to class and not to miss the announcements.
- 5.
- Grading:
Since this is a lab course, your grade will depend primarily upon your
performance in lab assignments that are completed on time. The weights
for the different labs are given in the quarter schedule at the end of
the syllabus.
You will be required to demo your simulation run to the TA during the TA office/lab hours. The TA will run several test cases on your design, so make sure that you have tested your design completely before you are ready to demo it. Your grade will depend on the number of test cases that perform satisfactorily on your model. Your final grade will be based on your cumulative performance on the lab assignments and the final completion of the processor or ASIC.
- 6.
- Late Policy:
No late assignments will be accepted. It is your responsibility to schedule
your time around interviews etc. that you may have to go for. We will be
handing out lab assignments well in advance, so there should be no excuse
for late work. In the case of extenuating circumstances, see the instructor.
- 7.
- Drop Policy:
Students will not be allowed to drop the course after the seventh week of
instruction.
- 8.
- Lab Policy:
No students may modify the system software on the workstations in any way.
Students caught modifying the software will be subject to discipline as
outlined for malicious conduct in the university regulations.
Any students caught putting a program containing a virus on any computer will be subject to discipline as outlined for malicious conduct in the university regulations.
Theft of software from the systems is subject to course expulsion and possible criminal charges.
- 9.
- Lab Guidelines:
Always design your system on paper and think of your modelling strategy
before writing the VHDL code. This saves time and lets others use the
computers more productively.
Organize your design as library directories, so that they can be used in later assignments.
Make sure that your design submissions have your name, ID#, the date written on them.
You may be required to give a demo of a completed assignment to the TA. In addition, most lab assignments require a short write-up. Details will be provided in the lab handouts.
Each students should read the bulletin board, ics.155b, for announcements etc. Students are responsible for reading this bulletin board as lab discussions, corrections and modifications will be posted there outside of class meetings.