In this assignment, you will be developing a structural model for the DCT chip in VHDL. You are provided with a primitive Register Transfer (RT) component library. The VHDL model and the delay for each component is given. You will be instantiating components from the library and developing the chip model. You will learn the hierarchial design methodology in structural VHDL by developing and simulating models for the DCT chip.

This assignment has 2 parts. The first part is due 1 week from now (on June 3rd) and the second part is due 4 weeks from now (on June 12th, the last day the lab is open).

 

Figure 1: The DCT Chip

As shown in Figure 1, the structural view of the sequential design is decomposed into two parts, namely controller and datapath. The controller generates a set of control signals grouped as control word which controls the datapath. The datapath send a status word to the controller. The status signals helps in determining the next state and control signals generated. In the DCT example, the status word consists of the nine bits of the count register.

The top-level view of the DCT chip is shown in Figure 2. Note that the entire design has been partitioned into a controller and a datapath. The controller is in-turn modelled as shown in Figure 3. The controller is a finite-state machine with a State Register (described in the str.vhd file), Next State and Output Logic (described in the logic.vhd file).

 

Figure 2: Hierarchical view of the DCT chip

 

Figure 3: The controller for the DCT chip

In the first part of this lab assignment, you are required to figure out the datapath interconnections given the controller model and the unconnected datapath shown in Figure 4 executing the behavior given in Figure 5. You are required to finish an incomplete datapath schematic drawn in Synopsys Schematic Editor. For this part you just need to complete the schematic. All other parts of the DCT chip are provided and are correct. Finish the wiring and generate the VHDL code for the datapath. The code for the datapath can generated easily using the Synopsys tools if the datapath has been wired correctly (as done in the first tutorial assignment). Compile the code for the datapath, the controller with the test bench together and observe the simulation results.

 

Figure 4: Unfinished Datapath schematic drawn in Synopsys Schematic Editor

 

Figure 5: ASM chart for the sequential behavior of the DCT chip

In Lab assignment 2, you used Chaining, Multicycling and Loop Unrolling to improve the performance. In Lab assignment 3, you used Pipelining to further improve the performance of the design. In this part, you will design and simulate a structural model for the controller and the datapath for the best optimized DCT design that you developed in assignment 3. You may need to change the datapath schematic that you completed for part 1 of this assigment. The controller model will then need to be changed inorder to provide the correct control signals for the optimized design.

1. Familiarize yourself with the design (controller and datapath) given in the Appendix.
2. Study the VHDL model for each component given in the Appendix and the files (ram.vhd, rom.vhd, reg.vhd, str.vhd etc. Pay attention to the delay of each component. Study the higher level models as well as their symbols. Understand the hierarchy of the structural model of the DCT chip.
3. Read the logic.vhd file carefully. This file has the Next State and Output Logic for the controller. Go through these files and figure out the wiring of the datapath schematic according to the given controller model.
4. Write the structural model of the controller and the datapath using components given and the diagrams provided. Use the Synopsys Schematic Editor in the Synopsys Graphical Editor to wire the datapath and generate the VHDL source code for the datapath.
5. Generate the VHDL code for the wired datapath using the appropriate commands in the Synopsys Graphical Environment, compile and simulate the design. In order to find all the critical paths, determine the maximal delay and the minimal clock period to execute your design.

1. Repeat Lab 4 for your best optimized design, from the previous assignments, which is obtained via techniques like Loop Unrolling, Chaining, Multicycling and Pipeling.
2. Modify the datapath schematic for the new design with the optimizations that you come up with.
3. Modifiy the controller to generate the correct control signals for the new design. Add/remove components from the datapath of Lab 4 and change the component models if required.

1. Printout of the the complete wired datapath schematic (for the sequential design without optimizations) along with 2 pages of waveforsms that show the performance and correctness of the result.
2. Do not submit any code that was not changed by you in this lab assignment.
3. Mail an electronic copy of your VHDL code (datapath schematic) to the TA.
4. Give an estimate of the number of hours you spent inside and outside the lab, including the write-up.
5. Put your name and student ID on the submissions.

1. List all the optmization techniques that you have use for improving performance.
2. Sumbit the new datapath schematic and the VHDL code for the new controller. If you modified the ports, delays, component symbols, functionality of the component models given or any other files given to you, document the modifications and submit the new compoment model/VHDL code or whatever was changed.
3. Do not submit any code that was not changed by you in this lab assignment.
4. Mail an electronic copy of your VHDL code (datapath schematic and the controller) to the TA.
5. Write a short discussion on the optimizations done and the performance of the chip versus hardware costs etc.
6. Give an estimate of the number of hours you spent inside and outside the lab, including the write-up.
7. Put your name and student ID on the submissions.

A.1   comp.vhd

A.2   adder.vhd

A.3   multiplier.vhd

A.4   mux2x1.vhd

A.5   reg.vhd

A.6   counter.vhd

A.7   rom.vhd

A.8   ram.vhd

A.9   controller.vhd

A.10   str.vhd

A.11   logic.vhd

A.12   clock_gr.vhd