In this lab, you'll be developing a VHDL model for ASM chart of the DCT chip and explore several design alternatives.

In Lab 1, we have focused on the following issues:

1. The timing protocol of the DCT chip - how the chip communicates with the outside world.
2. The test bench - how we verify the VHDL model.
3. The behavioral model - what the DCT computes.

Note that in Lab 1 we only specified the behavior of the chip without any commitment to chip implementation. In order for the chip to be implemented in hardware, we have to add the notion of time, that is, we have to specify when each operation is executed.

The ``WHEN'' information is derived from two constraints, namely, data dependencies and resource constraints. Because of the data dependencies inherent in the description, Operations must be performed in series. Because of the resource constraints, the operations that use the same resources must be serialized, that is, they can never be executed at the same time. The determination of the ``WHEN'' information is generally referred as scheduling.

After scheduling, we can construct an ASM chart, which you have learned from ICS 151 and covered in more detail in ICS 152. For those of you who are not familiar with ASM charts, we are giving a short refreshment course below.

 

Figure 1: An ASM Chart Example

There are 4 key constructs in ASM chart (Figure 1), namely the state box, decision box, conditional box, and block. RT operations can be specified in both the state and conditional boxes. The decision boxes help to specify the conditions under which state transitions and RT operations inside the conditional boxes occur. Note that an ASM chart can be naturally partitioned into a set of blocks, in which each block contains exactly one state box, a tree of decision and conditional boxes, and several exit paths which lead to other blocks.

In this lab, we will explore several design alternatives starting with the most sequential design. The VHDL code for the sequential design is also provided below in order to illustrate how to write VHDL models for ASM charts. You are responsible for improving performance of the present ASM chart, developing a new high-performance chart and its VHDL model.

 

Figure 2: ASM Chart for the Sequential Design

 

Figure 3: Illustration of Indexing

As shown in Figure 2, mapping from behavioral model to the most sequential design is pretty straightforward. Basically, we allocate 1 clock cycle for each set of operations that do not dependent on each other.

If you look at the source listing, you can see VHDL process used to model the ASM chart. The behaviors associated with each block in ASM chart are grouped into a state. There is a variable ``State'' to keep track of where the current state is. The process is activated upon every rising edge of the clock. Only those operations in the current state are executed in the present clock cycle.

As we discussed in class, several optimization techniques can be applied to the sequential design in order to speed it up:

1. loop unrolling.
2. chaining
3. multicycling

1. Read this handout and copy of the lecture notes/slides (available on the class web page).
2. Study the ASM chart and the VHDL code for sequential design.
3. Redo the ASM chart by applying the following optimization techniques to obtain performance improvement: (1) loop unrolling; (2) chaining; (3) multicycling.
4. Derive the VHDL model for your ASM chart.
5. Estimate the performance in terms of number of clock cycles.
6. Your report : The write-up should include (1) Your ASM chart and a brief interpretation of the VHDL model; (2) Your complete source listing; (3) Your estimated performance and the waveform that can verify your estimated performance.
7. Give an estimate of the number of hours you spent inside and outside the lab, including the write-up.
8. Put your name and student ID on the submissions.

   sequential.vhd

   clock.vhd

   tb.vhd