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ICCAD 2001 :
[ <A HREF="iccadabs.htm">Abstracts</A> ]
[ <A HREF="iccadses.htm">Session Index</A> ]
[ <A HREF="iccadai.htm">Author Index</A> ]</H3>
<HR>
<H2>ICCAD 2001 Table of Contents</H2>
<B>
Sessions:
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1d">1D</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3d">3D</A>]
[<A HREF="#panel1">Panel</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess4c">4C</A>]
[<A HREF="#sess4d">4D</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6d">6D</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7d">7D</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess8c">8C</A>]
[<A HREF="#sess8d">8D</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9d">9D</A>]
[<A HREF="#sess10a">10A</A>]
[<A HREF="#sess10b">10B</A>]
[<A HREF="#sess10c">10C</A>]
[<A HREF="#sess11a">11A</A>]
<P>
<A HREF="../../pdffiles/foreword.pdf">Foreword</A><BR>
<A HREF="../../pdffiles/confcom.pdf">Conference Committee</A><BR>
<A HREF="../../pdffiles/techcom.pdf">Technical Program Committee</A><BR>
<A HREF="../../pdffiles/reviewer.pdf">Reviewers</A><BR>
<A HREF="../../pdffiles/keynote.pdf">Keynote</A><BR>
<A HREF="../../pdffiles/tut1.pdf">Tutorial 1: Electrical-Integrity
Design and Verification for Digital and Mixed-Signal Systems-On-A-Chip
</A><BR>
<A HREF="../../pdffiles/tut2.pdf">Tutorial 2: Boolean Satisfiability
Solving and Its Application in Equivalence
and Model Checking</A><BR>
<A HREF="../../pdffiles/tut3.pdf">Tutorial 3: Low-Power/Low-Energy
Embedded Software: What, Why and How? </A><BR>
<A HREF="../../pdffiles/tut4.pdf">Tutorial 4: Optimization Strategies
for Physical Synthesis and Timing Closure</A><P>
</B>
<HR>
<H2>Session 1A: <A HREF="iccadabs.htm#sess1a" NAME="sess1a">
Dynamic Verification
</A></H2>
<I>
Moderators: Jay Lawrence, Cadence Design Systems, Inc., Chelmsford, MA<BR>
Kunle Olokotun, Stanford University, Stanford, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.1 Static Scheduling of Multi-Domain Memories For Functional Verification [p. 2]
<DD><I>
Murali Kudlugi, Charles Selvidge, Russell Tessier
</I><P>
<DT>
<A HREF="iccadabs.htm#01a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.2 A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor
Systems [p. 10]
<DD><I>
Scott A. Taylor, Carl Ramey, Craig Barner, David Asher
</I><P>
<DT>
<A HREF="iccadabs.htm#01a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.3 Predicting the Performance of Synchronous Discrete Event Simulation Systems [p. 18]
<DD><I>
Jinsheng Xu, Moon Jung Chung
</I><P>
</DL>
<HR>
<H2>Session 1B: <A HREF="iccadabs.htm#sess1b" NAME="sess1b">
System-Level Exploration and Design
</A></H2>
<I>
Moderators: Yanbing Li, Synopsys, Inc., Mountain View, CA<BR>
Xiaobo (Sharon) Hu, University of Notre Dame, Notre Dame, IN
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.1System-Level Exploration for Pareto-Optimal Configurations in Parameterized
Systems-on-a-Chip [p. 25]
<DD><I>
Tony D. Givargis, Frank Vahid, Joerg Henkel
</I><P>
<DT>
<A HREF="iccadabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.2 System Level Design with Spade: an M-JPEG Case Study [p. 31]
<DD><I>
Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere
</I><P>
<DT>
<A HREF="iccadabs.htm#01b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.3 NetBench: A Benchmarking Suite for Network Processors [p. 39]
<DD><I>
Gokhan Memik, William H. Mangione-Smith, Wendong Hu
</I><P>
</DL>
<HR>
<H2>Session 1C: <A HREF="iccadabs.htm#sess1c" NAME="sess1c">
Interconnect Planning
</A></H2>
<I>
Moderators: Robi Dutta, Synopsys, Inc., Mountain View, CA<BR>
Chung-Kuan Cheng, University of California at San Diego, La Jolla, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.1 Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion [p. 44]
<DD><I>
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
</I><P>
<DT>
<A HREF="iccadabs.htm#01c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.2 A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints [p. 49]
<DD><I>
Xiaoping Tang, Ruiqi Tian, Hua Xiang, D.F. Wong
</I><P>
<DT>
<A HREF="iccadabs.htm#01c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.3 Bus Encoding to Prevent Crosstalk Delay [p. 57]
<DD><I>
Bret M. Victor, Kurt Keutzer
</I><P>
</DL>
<HR>
<H2>Session 1D: <A HREF="iccadabs.htm#sess1d" NAME="sess1d">
Analog Macromodeling
</A></H2>
<I>
Moderators: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA<BR>
Henry Chang, Cadence Design Systems, Inc., San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.1 Behavioral Modeling of Analog Circuits by Wavelet Collocation Method [p. 65]
<DD><I>
Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
</I><P>
<DT>
<A HREF="iccadabs.htm#01d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.2 Simulation-Based Automatic Generation of Signomial and Posynomial
Performance Models for Analog Integrated Circuit Sizing [p. 70]
<DD><I>
Walter Daems, Georges Gielen, Willy Sansen
</I><P>
<DT>
<A HREF="iccadabs.htm#01d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.3 Power Grid Transient Simulation in Linear Time Based on
Transmission-Line-Modeling Alternating-Direction-Implicit Method [p. 75]
<DD><I>
Yu-Min Lee, Charlie Chung-Ping Chen
</I><P>
</DL>
<HR>
<H2>Session 2A: <A HREF="iccadabs.htm#sess2a" NAME="sess2a">
Embedded Tutorial: Platform-Based Designs
</A></H2>
<I>
Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA
</I>
<HR>
<H2>Session 2B: <A HREF="iccadabs.htm#sess2b" NAME="sess2b">
Embedded Tutorial: VLSI Microsystems: The Power of Many
</A></H2>
<I>
Moderator: Matton Kamon, Conventor, Inc., Cambridge, MA
</I>
<HR>
<H2>Session 3A: <A HREF="iccadabs.htm#sess3a" NAME="sess3a">
Sequential Synthesis
</A></H2>
<I>
Moderators: Hamid Savoj, Magma Design Automation, Inc., Cupertino, CA<BR>
Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.1 Sequential SPFDs [p. 84]
<DD><I>
Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
</I><P>
<DT>
<A HREF="iccadabs.htm#03a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.2 On the Optimization Power of Redundancy Addition and Removal Techniques for
Sequential Circuits [p. 91]
<DD><I>
Enrique San Mill‡n, Luis Entrena, JosŽ Alberto Espejo
</I><P>
<DT>
<A HREF="iccadabs.htm#03a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.3 Placement Driven Retiming with a Coupled Edge Timing Model [p. 95]
<DD><I>
Ingmar Neumann, Wolfgang Kunz
</I><P>
<DT>
<A HREF="iccadabs.htm#03a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.4 Solution of Parallel Language Equations for Logic Synthesis [p. 103]
<DD><I>
Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alex Petrenko, Alberto L.
Sangiovanni-Vincentell
</I><P>
</DL>
<HR>
<H2>Session 3B: <A HREF="iccadabs.htm#sess3b" NAME="sess3b">
Compiler Techniques in System Level Design
</A></H2>
<I>
Moderators: Radu Marculescu, Carnegie Mellon University, Pittsburgh, PA<BR>
Grant Martin, Cadence Design Systems, Inc., San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.1 CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors [p. 112]
<DD><I>
Cagdas Akturan, Margarida F. Jacome
</I><P>
<DT>
<A HREF="iccadabs.htm#03b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.2 Software-Assisted Cache Replacement Mechanisms for Embedded Systems [p. 119]
<DD><I>
Prabhat Jain, Srinivas Devadas, Daniel Engels, Larry Rudolph
</I><P>
<DT>
<A HREF="iccadabs.htm#03b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.3 Instruction Generation for Hybrid Reconfigurable Systems [p. 127]
<DD><I>
Ryan Kastner, Seda Ogrenci-Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
</I><P>
</DL>
<HR>
<H2>Session 3C: <A HREF="iccadabs.htm#sess3c" NAME="sess3c">
Routing Architecture and Techniques for FPGAs
</A></H2>
<I>
Moderators: Majid Sarrafzadeh, University of California, Los Angeles, CA<BR>
Rajeev Jayaraman, Xilinx, Inc., San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.1 Interconnect Resource-Aware Placement for Hierarchical FPGAs [p. 132]
<DD><I>
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowsk
</I><P>
<DT>
<A HREF="iccadabs.htm#03c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.2 A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation [p. 137]
<DD><I>
Nak-Woong Eum, Taewhan Kim, Chong Min Kyung
</I><P>
<DT>
<A HREF="iccadabs.htm#03c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.3 A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs [p. 144]
<DD><I>
Vinay Verma, Shantanu S. Dutt
</I><P>
</DL>
<HR>
<H2>Session 3D: <A HREF="iccadabs.htm#sess3d" NAME="sess3d">
Interconnect Performance and Reliability Optimization
</A></H2>
<I>
Moderators: David D. Ling, IBM Corp. TJ Watson Research Center,
Yorktown Heights, NY<BR>
Ken Kundert, Cadence Design Systems, Inc., San Jose, CA
</I><P>
<DL>
<DT>
<A HREF="iccadabs.htm#03d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.1 Area Minimization of Power Distribution Network Using Efficient Nonlinear
Programming Techniques [p. 153]
<DD><I>
Xiaohai Wu, Xianlong Hong, Yici Cai, C.K. Cheng, Jun Gu, Wayne Dai
</I><P>
<DT>
<A HREF="iccadabs.htm#03d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.2 Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets [p. 158]
<DD><I>
Kaustav Banerjee, Amit Mehrotra
</I><P>
<DT>
<A HREF="iccadabs.htm#03d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.3 Compact Modeling and SPICE-Based Simulation for Electrothermal
Analysis of Multilevel ULSI Interconnects [p. 165]
<DD><I>
TingYen Chiang, Kaustav Banerjee, Krishna C. Saraswat
</I><P>
</DL>
<HR>
<H2><A HREF="iccadabs.htm#panel1" NAME="panel1">
Panel:
</A></H2>
<I>
Moderator: Andreas Kuehlmann, Cadence Berkeley Laboratories, Berkeley, CA<BR>
Panelists: Robert W. Dutton, Paul Franzon, Seth C. Goldstein,
Philip Luekes, Eric Parker, Thomas N. Theis
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#panel1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/panel1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Will Nanotechnology Change the Way We Design and Verify Systems? [p. 174]
</DL>
<HR>
<H2>Session 4A: <A HREF="iccadabs.htm#sess4a" NAME="sess4a">
Circuit Structure in Fromal Verification
</A></H2>
<I>
Moderators: Masahiro Fujita, University of Tokyo, Tokyo, Japan<BR>
Vigyan Singal, Tempus Fujit, Berkeley, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4A.1 Min-Area Retiming on Dynamic Circuit Structures [p. 176]
<DD><I>
Jason Baumgartner, Andreas Kuehlmann
</I><P>
<DT>
<A HREF="iccadabs.htm#04a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4A.2 Verification of Integer Multipliers on the Arithmetic Bit Level [p. 183]
<DD><I>
Dominik A. Stoffel, Wolfgang Kunz
</I><P>
<DT>
<A HREF="iccadabs.htm#04a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4A.3 Induction-Based Gate-Level Verification of Multipliers [p. 190]
<DD><I>
Ying-Tsai Chang, Kwang-Ting(Tim) Cheng
</I><P>
</DL>
<HR>
<H2>Session 4B: <A HREF="iccadabs.htm#sess4b" NAME="sess4b">
System Level Power and Performance Modeling`
</A></H2>
<I>
Moderators: Wayne Wolf, Mediaworks Technology, Schaumberg, IL<BR>
Preeti Panda, Synopsys, Inc., Mountain View, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4B.1 An Assembly-Level Execution-Time Model for Pipelined Architectures [p. 195]
<DD><I>
Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
</I><P>
<DT>
<A HREF="iccadabs.htm#04b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4B.2 Improving Memory Energy Using Access Pattern Classification [p. 201]
<DD><I>
Mahut T. Kandemir, Ugur Sezer, Victor Delaluz
</I><P>
<DT>
<A HREF="iccadabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4B.3 System-Level Power/Performance Analysis of Portable Multimedia Systems
Communicating over Wireless Channels [p. 207]
<DD><I>
Radu Marculescu, Amit Nandi, Luciano Lavagno, Alberto Sangiovanni-Vincentelli
</I><P>
</DL>
<HR>
<H2>Session 4C: <A HREF="iccadabs.htm#sess4c" NAME="sess4c">
Topics in Physical Synthesis
</A></H2>
<I>
Moderators: Andrew B. Kahng, University of California at San Diego,
La Jolla, CA<BR>
Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4C.1 Congestion Aware Layout Driven Logic Synthesis [p. 216]
<DD><I>
Thomas Kutzschebauch, Leon Stok
</I><P>
<DT>
<A HREF="iccadabs.htm#04c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4C.2 Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement [p. 224]
<DD><I>
Wilsin Gosti, Sunil Khatri, Alberto Sangiovanni-Vincentelli
</I><P>
<DT>
<A HREF="iccadabs.htm#04c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4C.3 An Algorithm for Simultaneous Pin Assignment and Routing [p. 232]
<DD><I>
Hua Xiang, Xiaoping Tang, D.F. Wong
</I><P>
</DL>
<HR>
<H2>Session 4D: <A HREF="iccadabs.htm#sess4d" NAME="sess4d">
Model Order Reduction
</A></H2>
<I>
Moderators: Eli Chiprout, Intel Corp., Chandler, AZ<BR>
Andreas C. Cangellaris, University of Illinois, Urbana, IL
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4D.1 Techniques for Including Dielectrics when Extracting Passive
Low-Order Models of High Speed Interconnect [p. 240]
<DD><I>
Luca Daniel, Alberto Sangiovanni-Vincentelli, Jacob K. White
</I><P>
<DT>
<A HREF="iccadabs.htm#04d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4D.2 A Convex Programming Approach to Positive Real Rational Approximation [p. 245]
<DD><I>
Carlos P. Coelho, Joel R. Phillips, Luis M. Silveira
</I><P>
<DT>
<A HREF="iccadabs.htm#04d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
4D.3 A Trajectory Piecewise-Linear Approach to Model Order Reduction and
Fast Simulation of Nonlinear Circuits and Micromachined Devices [p. 252]
<DD><I>
Michal Rewienski, Jacob K. White
</I><P>
</DL>
<HR>
<H2>Session 5A: <A HREF="iccadabs.htm#sess5a" NAME="sess5a">
Embedded Tutorial: Embedded Software and Systems
</A></H2>
<I>
Moderators: Rolf Ernst, Technical University of Braunschweig,
Braunschweig, Germany<BR>
Francky Catthoor, IMEC, Leuven, Belgium
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.1 Low Power System Scheduling and Synthesis [p. 259]
<DD><I>
Niraj K. Jha
</I><P>
<DT>
<A HREF="iccadabs.htm#05a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.3 Integral Design Representations for Embedded Systems [p. 264]
<DD><I>
Lothar Thiele
</I><P>
<DT>
<A HREF="iccadabs.htm#05a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.4 Optimisation Problems for Dynamic Concurrent Task-Based Systems [p. 265]
<DD><I>
D. Verkest, P. Yang, C. Wong, P. Marchal
</I><P>
</DL>
<HR>
<H2>Session 5B: <A HREF="iccadabs.htm#sess5b" NAME="sess5b">
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal
and RF IC Design [p. 270)
</A></H2>
<I>
Moderator: Georges Gielen, Katholieke University, Leuven, Belgium<BR>
Domine Leenaerts, Rob A. Rutenbar, Georges Gielen
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
</DL>
<HR>
<H2>Session 6A: <A HREF="iccadabs.htm#sess6a" NAME="sess6a">
BDDs and SAT
</A></H2>
<I>
Moderators: Alan J. Hu, University of British Columbia, Vancouver, BC, Canada<BR>
Rajeev Ranjan, Real Intent, Santa Clara, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.1 Efficient Conflict Driven Learning in Boolean Satisfiability Solver [p. 279]
<DD><I>
Lintao Zhang, Conor Madigan, Matthew Moskewicz, Sharad Malik
</I><P>
<DT>
<A HREF="iccadabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.2 Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs [p. 286]
<DD><I>
Aarti Gupta, Zijiang Yang, Pranav N. Ashar, Lintao Zhang, Sharad Malik
</I><P>
<DT>
<A HREF="iccadabs.htm#06a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.3 Non-linear Quantification Scheduling in Image Computation [p. 293]
<DD><I>
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, Jim Kukula, Tom Shiple,
Helmut Veith, Dong Wang
</I><P>
</DL>
<HR>
<H2>Session 6B: <A HREF="iccadabs.htm#sess6b" NAME="sess6b">
Convergence of Abstractions in High-Level Synthesis
</A></H2>
<I>
Moderators: Sandeep Shukla, University of California, Irvine, CA<BR>
Francky Catthoor, IMEC, Leuven, Belgium
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.1 Symbolic Algebra and Timing Driven Data-flow Synthesis [p. 300]
<DD><I>
Armita Peymandoust, Giovanni De Micheli
</I><P>
<DT>
<A HREF="iccadabs.htm#06b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.2 Application-Driven Processor Design Exploration for Power-Performance
Trade-off Analysis [p. 306]
<DD><I>
Diana Marculescu, Anoop Iyer
</I><P>
<DT>
<A HREF="iccadabs.htm#06b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.3 A System for Synthesizing Optimized FPGA Hardware from MATLAB [p. 314]
<DD><I>
Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee
</I><P>
<DT>
<A HREF="iccadabs.htm#06b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.4 Behavior-to-Placed RTL Synthesis with Performance-Driven Placement [p. 320]
<DD><I>
Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi
</I><P>
</DL>
<HR>
<H2>Session 6C: <A HREF="iccadabs.htm#sess6c" NAME="sess6c">
Signal Integrity and Clock Design
</A></H2>
<I>
Moderators: Cheng-Kok Koh, Purdue University, West Lafayette, IN<BR>
Tong Gao, Monterey Design Systems, Inc., Sunnyvale, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.1 Formulae and Applications of Interconnect Estimation Considering
Shield Insertion and Net Ordering [p. 327]
<DD><I>
James D.Z Ma, Lei He
</I><P>
<DT>
<A HREF="iccadabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.2 Hybrid Structured Clock Network Construction [p. 333]
<DD><I>
Haihua Su, Sachin Sapatnekar
</I><P>
<DT>
<A HREF="iccadabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.3 CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune
Precharge-Evaluate Logic [p. 337]
<DD><I>
Yonghee Im, Kaushik Roy
</I><P>
</DL>
<HR>
<H2>Session 6D: <A HREF="iccadabs.htm#sess6d" NAME="sess6d">
Analog Synthesis
</A></H2>
<I>
Moderators: Koen Lampaert, Mindspeed Technology, Newport Beach, CA
Henry Chang, Cadence Design Systems, Inc., San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.1 The Sizing Rules Method for Analog Integrated Circuit Design [p. 343]
<DD><I>
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich
</I><P>
<DT>
<A HREF="iccadabs.htm#06d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.2 ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits [p. 350]
<DD><I>
Michael J. Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung,
Rob A. Rutenbar, L. Richard Carley
</I><P>
<DT>
<A HREF="iccadabs.htm#06d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.3 A Layout-Aware Synthesis Methodology for RF Circuits [p. 358]
<DD><I>
Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges Gielen, Willy Sansen
</I><P>
</DL>
<HR>
<H2>Session 7A: <A HREF="iccadabs.htm#sess7a" NAME="sess7a">
Manufacturing Test: Stuck-at to Crosstalk
</A></H2>
<I>
Moderators: Sujit Dey, University of California at San Diego, La Jolla, CA<BR>
Yervant Zorian, LogicVision, Inc., San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.1 On Identifying Don't Care Inputs of Test Patterns for Combinational
Circuits [p. 364]
<DD><I>
Seiji Kajihara, Kohei Miyase
</I><P>
<DT>
<A HREF="iccadabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.2 REDI: An Efficient Fault Oriented Procedure to Identify Redundant
Faults in Combinational Logic Circuits [p. 370]
<DD><I>
Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
</I><P>
<DT>
<A HREF="iccadabs.htm#07a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.3 Crosstalk Fault Detection by Dynamic Idd [p. 375]
<DD><I>
Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota
</I><P>
</DL>
<HR>
<H2>Session 7B: <A HREF="iccadabs.htm#sess7b" NAME="sess7b">
Architecture Oriented Scheduling
</A></H2>
<I>
Moderators: Miodrag Potkonjak, University of California, Los Angeles, CA<BR>
Kazutoshi Wakabayashi, NEC Corp., Kawasaki, Japan
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.1 Color Permutation: An Iterative Algorithm for Memory Packing [p. 380]
<DD><I>
Jianwen Zhu, Edward S. Rogers, Sr.
</I><P>
<DT>
<A HREF="iccadabs.htm#07b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.2 Constraint Satisfaction for Relative Location Assignment and Scheduling [p. 384]
<DD><I>
Carlos Alba-Pinto, Bart Mesman, Jochen Jess
</I><P>
<DT>
<A HREF="iccadabs.htm#07b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.3 A Super-Scheduler for Embedded Reconfigurable Systems [p. 391]
<DD><I>
S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M. Sarrafzade
</I><P>
</DL>
<HR>
<H2>Session 7C: <A HREF="iccadabs.htm#sess7c" NAME="sess7c">
New Techniques in Routing
</A></H2>
<I>
Moderators: Jo Dale Carothers, University of Arizona, Tucson, AZ<BR>
Amir H. Farrahi, IBM Corp. TJ Watson Research Center, Yorktown Heights, NY
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.1 Multilevel Approach to Full-Chip Gridless Routing [p. 396]
<DD><I>
Jason Cong, Jie Fang, Yan Zhang
</I><P>
<DT>
<A HREF="iccadabs.htm#07c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.2 A Force-Directed Maze Router [p. 404]
<DD><I>
Fan Mo, Abdallah Tabbara, Robert K. Brayton
</I><P>
<DT>
<A HREF="iccadabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.3 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate
and Reliability Control [p. 408]
<DD><I>
Charles Alpert, Andrew B. Kahng, Bao Liu, Ion Mandoiu, Alexander Zelikovsky
</I><P>
</DL>
<HR>
<H2>Session 7D: <A HREF="iccadabs.htm#sess7d" NAME="sess7d">
Issues in Substrate Coupling
</A></H2>
<I>
Moderators: Mattan Kamon, Coventor, Inc., Cambridge, MA<BR>
Kenneth L. Shepard, Columbia University, New York, NY
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.1 Highly Accurate Fast Methods for Extraction and Sparsification
of Substrate Coupling Based on Low-Rank Approximation
[p. 417]
<DD><I>
Joe Kanapka, Jacob White
</I><P>
<DT>
<A HREF="iccadabs.htm#07d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.2 Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate [p. 424]
<DD><I>
Minqing Liu, Tiejun Yu, Wayne W.-M. Dai
</I><P>
<DT>
<A HREF="iccadabs.htm#07d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.3 Simulation Approaches for Strongly Coupled Interconnect Systems [p. 430]
<DD><I>
Joel R. Phillips, L. Miguel Silveira
</I><P>
</DL>
<HR>
<H2>Session 8A: <A HREF="iccadabs.htm#sess8a" NAME="sess8a">
Combinational Optimization
</A></H2>
<I>
Moderators: Olivier Coudert, Monterey Design Systems, Inc., Sunnyvale, CA<BR>
Tiziano Villa, Parades Labs., Rome, Italy
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8A.1 BOOM ö A Heuristic Boolean Minimizer [p. 439]
<DD><I>
Jan Hlavicka, Petr Fiser
</I><P>
<DT>
<A HREF="iccadabs.htm#08a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8A.2 Faster SAT and Smaller BDDs via Common Function Structure [p. 443]
<DD><I>
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
</I><P>
<DT>
<A HREF="iccadabs.htm#08a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8A.3 Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass
Transistor Logic Circuits
[p. 449]
<DD><I>
Rupesh S. Shelar, Sachin S. Sapatnekar
</I><P>
<DT>
<A HREF="iccadabs.htm#08a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8A.4 A Probabilistic Constructive Approach to Optimization Problems [p. 453]
<DD><I>
Jennifer L. Wong, Farinzaz Koushanfar, Seapahn Meguerdichian,
Miodrag Potkonjak
</I><P>
</DL>
<HR>
<H2>Session 8B: <A HREF="iccadabs.htm#sess8b" NAME="sess8b">
Real Time Scheduling and Performance Analysis
</A></H2>
<I>
Moderators: Pai Chou, University of California, Irvine, CA<BR>
Luciano Lavagno, Cadence Berkeley Labs., Berkeley, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8B.1 Energy Efficient Real-Time Scheduling [p. 458]
<DD><I>
Amit Sinha, Anantha P. Chandrakasan
</I><P>
<DT>
<A HREF="iccadabs.htm#08b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8B.2 Efficient Performance Estimation for General Real-Time Task Systems [p. 464]
<DD><I>
Hongchao (Stephanie) Liu, Xiaobo (Sharon) Hu
</I><P>
<DT>
<A HREF="iccadabs.htm#08b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8B.3 Stars in VCC: Complementing Simulation with Worst-Case Analysis [p. 471]
<DD><I>
Felice Balarin
</I><P>
</DL>
<HR>
<H2>Session 8C: <A HREF="iccadabs.htm#sess8c" NAME="sess8c">
Power Analysis
</A></H2>
<I>
Moderators: Anirudh Devgan, IBM Corp., Austin, TX<BR>
Carlo Guardini, PDF Solutions, San Jose, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8C.1 Multigrid-Like Technique for Power Grid Analysis [p. 480]
<DD><I>
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
</I><P>
<DT>
<A HREF="iccadabs.htm#08c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8C.2 An Analytical High-Level Battery Model for Use in Energy Management
of Portable Electronic Systems
[p. 488]
<DD><I>
Daler N. Rakhmatov, Sarma B.K. Vrudhula
</I><P>
<DT>
<A HREF="iccadabs.htm#08c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8C.3 Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization [p. 494]
<DD><I>
J.L. Rossello, Jaume Segura
</I><P>
</DL>
<HR>
<H2>Session 8D: <A HREF="iccadabs.htm#sess8d" NAME="sess8d">
Timing and Noise Analysis
</A></H2>
<I>
Moderators: Tim Burks, Magma Design Automation, Inc., Cupertino, CA<BR>
Florentin Dartu, Intel Corp., Hillsboro, OR
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8D.1 A Symbolic Simulation-Based Methodology for Generating Black-Box
Timing Models of Custom Macrocells
[p. 501]
<DD><I>
Clayton McDonald, Randal E. Bryant
</I><P>
<DT>
<A HREF="iccadabs.htm#08d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8D.2 On the Signal Bounding Problem in Timing Analysis [p. 507]
<DD><I>
Jin-Fuw Lee, D.L. Ostapko, Jeffery Soreff, C.K. Wong
</I><P>
<DT>
<A HREF="iccadabs.htm#08d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
8D.3 False-Noise Analysis using Logic Implications [p. 515]
<DD><I>
Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul,
Chanhee Oh, Vladimir Zolotov
</I><P>
</DL>
<HR>
<H2>Session 9A: <A HREF="iccadabs.htm#sess9a" NAME="sess9a">
System Level Test and Reliability
</A></H2>
<I>
Moderators: Bapi Vinnakota, University of Minnesota, Minneapolis, MN<BR>
Seiji Kajihara, Kyushu Institute of Technology, Iizuka, Japan
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.1 The Design and Optimization of SOC Test Solutions [p. 523]
<DD><I>
Erik Larsson, Zebo Peng, Gunnar Carlsson
</I><P>
<DT>
<A HREF="iccadabs.htm#09a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.2 Accurate CMOS Bridge Fault Modeling with Neural Network-Based
VHDL Saboteurs [p. 531]
<DD><I>
Don Shaw, Dhamin Al-Khalili, C™me Rozon
</I><P>
<DT>
<A HREF="iccadabs.htm#09a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.3 Algorithm Level Re-Computing - A Register Transfer Level
Concurrent Error Detection Technique [p. 537]
<DD><I>
Kaijie Wu, Ramesh Karri
</I><P>
</DL>
<HR>
<H2>Session 9B: <A HREF="iccadabs.htm#sess9b" NAME="sess9b">
Power Issues in High Level Synthesis
</A></H2>
<I>
Moderators: Sridevan Parameswaran, The University of New
South Wales, Kensington, Australia<BR>
Nikil Dutt, University of California, Irvine, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.1 Transient Power Management Through High Level Synthesis [p. 545]
<DD><I>
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha, Ganesh Lakshminarayana
</I><P>
<DT>
<A HREF="iccadabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.2 An Integrated Data Path Optimization for Low Power Based
on Network Flow Method
[p. 553]
<DD><I>
Chun-Gi Lyuh, Taewhan Kim, C.L. Liu
</I><P>
<DT>
<A HREF="iccadabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.3 What is the Limit of Energy Saving by Dynamic Voltage Scaling? [p. 560]
<DD><I>
Gang Qu
</I><P>
</DL>
<HR>
<H2>Session 9C: <A HREF="iccadabs.htm#sess9c" NAME="sess9c">
Advances in Placement
</A></H2>
<I>
Moderators: Jason Cong, University of California, Los Angeles, CA<BR>
Patrick Groeneveld, Magma Design Automation, Inc., Cupertino, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.1 Local Search for Final Placement in VLSI Design [p. 565]
<DD><I>
Oluf Faroe, David Pisinger, Martin Zachariase
</I><P>
<DT>
<A HREF="iccadabs.htm#09c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.2 Congestion Reduction During Placement Based on Integer Programming [p. 573]
<DD><I>
Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
</I><P>
<DT>
<A HREF="iccadabs.htm#09c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.3 Direct Transistor-Level Layout for Digital Blocks [p. 577]
<DD><I>
Prakash Gopalakrishnan, Rob A. Rutenbar
</I><P>
</DL>
<HR>
<H2>Session 9D: <A HREF="iccadabs.htm#sess9d" NAME="sess9d">
Interconnect Analysis and Extraction
</A></H2>
<I>
Moderators: Dennis M. Sylvester, University of Michigan, Ann Arbor, MI<BR>
Mustafa Celik, Monterey Design Systems, Inc., Sunnyvale, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.1 Model Reduction of Variable-Geometry Interconnects using
Variational Spectrally-Weighted Balanced Truncation [p. 586]
<DD><I>
Payam Heydari, Massoud Pedram
</I><P>
<DT>
<A HREF="iccadabs.htm#09d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.2 Improving the Robustness of a Surface Integral Formulation for
Wideband Impendance Extraction of 3D Structures
[p. 592]
<DD><I>
Zhenhai Zhu, Jingfang Huang, Ben Song, Jacob White
</I><P>
<DT>
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<A HREF="../../pdffiles/09d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.3 Practical Considerations in RLCK Crosstalk Analysis for Digital
Integrated Circuits
[p. 598]
<DD><I>
Steven C. Chan, K.L. Shepard
</I><P>
</DL>
<HR>
<H2>Session 10A: <A HREF="iccadabs.htm#sess10a" NAME="sess10a">
Don't Care Optimization and Boolean Matching
</A></H2>
<I>
Moderators: Yuji Kukimoto, Silicon Perspective Corp., Santa Clara, CA<BR>
Prabhakar Kudva, IBM Corp. TJ Watson Research
Center, Yorktown Heights, NY
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.1 Single-Pass Redundancy Addition and Removal[p. 606]
<DD><I>
Chih-Wei (Jim) Chang, Malgorzata Marek-Sadowska
</I><P>
<DT>
<A HREF="iccadabs.htm#10a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.2 Efficient Canonical Form for Boolean Matching of Complex Functions in
Large Libraries
[p. 610]
<DD><I>
Jovanka Ciric, Carl Sechen
</I><P>
<DT>
<A HREF="iccadabs.htm#10a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.3 Compatible Observability Donât Cares Revisited [p. 618]
<DD><I>
R.K. Brayton
</I><P>
</DL>
<HR>
<H2>Session 10B: <A HREF="iccadabs.htm#sess10b" NAME="sess10b">
Power Saving Techniques for Embedded Processors
</A></H2>
<I>
Moderators: Preeti Panda, Synopsys, Inc., Mountain View, CA<BR>
Tony Givargis, University of California, Irvine, CA
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.1 A Methodology for the Design of Application Specific Instruction
Set Processors (ASIP) using the Machine Description Language LISA
[p. 625]
<DD><I>
Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunner Braun,
Oliver Wahlen, Heinrich Meyr
</I><P>
<DT>
<A HREF="iccadabs.htm#10b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.2 Area and Power Reduction of Embedded DSP Systems using
Instruction Compression and Re-Configurable Encoding
[p. 631]
<DD><I>
Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
</I><P>
<DT>
<A HREF="iccadabs.htm#10b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.3 I-CoPES: Fast Instruction Code Placement for Embedded Systems
to Improve Performance and Energy Efficiency
[p. 635]
<DD><I>
Sri Parameswaran, Jšrg Henkel
</I><P>
</DL>
<HR>
<H2>Session 10C: <A HREF="iccadabs.htm#sess10c" NAME="sess10c">
Embedded Tutorial: IC Power Distribution Challenges
</A></H2>
<I>
Moderator: Farid Najm, University of Toronto, Toronto, ON, Canada
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10C.1 IC Power Distribution Challenges [p. 643]
<DD><I>
Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu
</I><P>
<DT>
<A HREF="iccadabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10C.2 Challenges in Power-Ground Integrity [p. 651]
<DD><I>
Shen Lin, Norman Chang
</I><P>
</DL>
<HR>
<H2>Session 11A: <A HREF="iccadabs.htm#sess11a" NAME="sess11a">
Panel: Automatic Hierarchical Design: Fantasy or Reality?
</A></H2>
<I>
Moderator: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA<BR>
Panelists: Olivier Coudert, Patrick Groeneveld, Juergen Koehl,
Scott Peterson, Vivek Raghavan, Naresh Soni
</I>
<DL>
<DT>
<A HREF="iccadabs.htm#sess11a"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/panel2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
11A.1 Automatic Hierarchical Design: Fantasy or Reality? [p. 656]
</DL>
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