12th Asia and South Pacific Design Automation Conference

ASP-DAC 2007

Date : Jan. 23-26 2007
Place: Pacifico Yokohama, Yokohama, Japan

Tutorials

Two full-day and four half-day tutorials will be presented in four parallel sessions on January 23, 2007. The tutorials are given by top experts in the fields and cover today's most important issues in system LSI design and EDA technologies : DFM, functional verification, low power, physical synthesis and embedded system design.

• Date: Tuesday, January 23, 2007 (9:30 - 17:00)
• Place: Pacifico Yokohama, Conference Center, 4F

• Chair: Makoto Ikeda (Univ. of Tokyo)

Tutorial 1 (Full Day), Tuesday, January 23, 9.30 - 17.00 (Room 411+412)

DFM Tools and Methodologies for 65nm and Below

Organizer:
Andrew B. Kahng - Univ. of California, San Diego and Blaze DFM, Inc., United States

Speakers:
N. S. Nagaraj - Texas Instruments, United States
Jean-Pierre Schoellkopf - STMicroelectronics, France
Mike Smayling - Applied Materials, United States
Ban P. Wong - Charterd Semiconductor, United States
Andrew B. Kahng - Univ. of California, San Diego and Blaze DFM, Inc., United States

Abstract:
Entering the 65nm node, today's DFM tools attempt to satisfy several basic objectives. To address the failure of "WYSIWYG" in sub-100nm process nodes, "shape" (x-y dimension) and "thickness" (z dimension) simulation technologies are being deployed. To address "uncontrollable variation", statistical analysis technologies (SSTA, statistical extraction, etc.) are being investigated. And, well-established internal technologies for defect-oriented yield analysis (critical area, pattern hotspot finding) and optimization (via/contact doubling, wire spreading, etc.) are being commoditized. The order of tool deployment has been as one would expect: (1) geometric criteria (through process window hot-spots, etc.) before electrical criteria (leakage, timing variation, etc.); (2) library and IP development use models before full-chip use models; and (3) analyses before optimizations.

How are such technologies applied to ensure the fastest library and RET development, the fastest process ramps, the highest yields? This tutorial will discuss DFM technologies and methodologies that provide high-ROI bridges between designers and the manufacturing process.

Part 1: Interactions between layout and manufacturability for devices
Part 2: Interactions between layout and manufacturability for interconnects
Part 3: Design of test structures and test chips to characterize FEOL and BEOL variability, and use of in-line metrology to inform modeling and cycles of yield learning
Part 4: Current DFM tools and methodologies, along with opportunities for improved DFM deployment
Part 5: New tools and futures

Tutorial 2 (Full Day), Tuesday, January 23, 9.30 - 17.00 (Room 413)

Functional Verification Planning and Management - The Road to Verification Closure is Paved with Good Intentions

Organizers:
Andrew Piziali - Cadence, United States
Avi Ziv - IBM, Israel

Speakers:
Andrew Piziali - Cadence, United States
Avi Ziv - IBM, Israel

Abstract:
This tutorial teaches the student state-of-the-art techniques and methodologies that are used in the industry today for planning, monitoring and assessing verification progress. Planning, monitoring and assessment of the verification process are essential for predictable, successful verification. Quantifying the scope of the verification problem, specifying its solution and measuring verification progress against this plan dramatically reduces schedule uncertainty and provides an adaptive framework for accommodating design and schedule changes. This planning process provides the information necessary to predict the state of the verification process for risk analysis and management. Overall, good planning, monitoring and assessment prevent late schedule and quality surprises.

Tutorial 3 (Half Day), Tuesday, January 23, 9.30 - 12.30 (Room 414+415)

Low Power CMOS Design:
The Fabrics: Research Front-End

Organizer:
Tadahiro Kuroda - Keio University, Japan

Speakers:
Hitoshi Wakabayashi - Sony, Japan
Tadahiro Kuroda - Keio University, Japan
Ankur Gupta - Cadence, United States
Luca Benini - Bologna University, Italy

Abstract:
This tutorial will cover research front-ends of low power CMOS design, including (1) process and device level, (2) circuit level, (3) EDA level, and (4) system level.

Tutorial 4 (Half Day), Tuesday, January 23, 14.00 - 17.00 (Room 414+415)

Low Power CMOS Design:
The Applications: State-of-the-Art Practice

Organizer:
Tadahiro Kuroda - Keio University, Japan

Speakers:
Toshihiro Hattori - Renesas, Japan
Atsuki Inoue - Fujitsu Laboratory, Japan
Masaya Sumita - Panasonic, Japan
Mototsugu Hamada - Toshiba, Japan

Abstract:
This tutorial will cover state-of-the-art practice of low power CMOS designs in various application fields, including (1) application processors, (2) ASICs, (3) digital consumer products, and (4) wireless communication chips.

Tutorial 5 (Half Day), Tuesday, January 23, 9.30 - 12.30 (Room 416+417)

Fast Physical Synthesis for Multi-Million Gate ASIC Designs

Organizer:
Charles J. Alpert - IBM, United States

Speakers:
Charles J. Alpert - IBM, United States

Abstract:
This tutorial presents new physical synthesis techniques that are designed to improve throughput. This tutorial discusses:

• Placement techniques: The tutorial discusses new approaches that make placement fast (such as multilevel clustering) and also modern force-directed placement techniques that have recently proven superior for obtaining high quality placements. The tutorial will also discuss the placement of multi-cycle latches.
• Innovative buffering techniques: The tutorial discusses new techniques for inserting buffers quickly (compared to traditional van Ginneken) and how to also handle modern routing congestion constraints.
• Legalization paradigm shift: This tutorial discusses a technique called diffusion that smoothly spreads out cells to handle these difficult legalization instances.
• The optimization model: No matter what kind of change is required, whether synthesis, repowering or buffering is required, the tool needs a mechanism to evaluate the change and then either accept or reject the solution, via an incremental static timing analysis tool. The tutorial will briefly cover this optimization model.
• Putting it all together: All the pieces still need to be assemble into a coherent physical synthesis flow. The tutorial presents ways to combine the techniques of electrical correction, critical path optimization, histogram compression, wirelength reduction, and area recovery into a coherent flow that can be used for timing closure. Insights into design techniques and strategies for interacting with physical synthesis flows will also be discussed.

Tutorial 6 (Half Day), Tuesday, January 23, 14.00 - 17.00 (Room 416+417)

Concepts and Tools for Practical Embedded System Design

Organizer:
Nikil Dutt - Univ. of California, Irvine, United States

Speakers:
Daniel Gajski - Univ. of California, Irvine, United States
Andreas Gerstlauer - Univ. of California, Irvine, United States
Samar Abdi - Univ. of California, Irvine, United States

Abstract:
The continuous increase in size, complexity and heterogeneity of embedded system (ES) designs has introduced new challenges in their modeling, synthesis and verification. The ES designs of today are being specified and developed at higher levels of abstraction such as transaction level to cope with their complexity. For ES implementation, the application must be mapped to the target platform. The higher level descriptions are then translated to platformaware RTL/C code that can be input to standard SW and EDA tools. All ES design descriptions also need to be verifiable to ensure their consistency and functional correctness.

In this tutorial, we will cover the key concepts and state of the art tools for ES design using industrial strength case studies such as MP3 player design. We will have in-depth presentations on the following topics:

1. Introduction and ES design requirements.
2. ES programming and modeling at specification and transaction levels.
3. Tools for implementation and verification of ES designs for different HW-SW platforms.
4. Tools for synthesis of HW, SWand interfaces from high level ES models.
5. Verification of ES designs using simulation and FPGA prototyping.
6. A roadmap for establishing an ES design science and tool flow.