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The 12th Asia and South Pacific Design Automation Conference

Session 8B Electrical Optimization in Floorplanning/Placement
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Room 413
Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), David Pan (Univ. of Texas, Austin, United States)

8B-1 (Time: 13:30 - 13:55)
TitleThermal-Aware 3D IC Placement Via Transformation
AuthorJason Cong, *Guojie Luo, Jie Wei, Yan Zhang (Univ. of California, Los Angeles, United States)
Pagepp. 780 - 785
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8B-2 (Time: 13:55 - 14:20)
TitleNoise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
AuthorFayez Mohamood, Michael Healy, Sung Kyu Lim, *Hsien-Hsin S. Lee (Georgia Tech, United States)
Pagepp. 786 - 791
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8B-3 (Time: 14:20 - 14:45)
TitleOn Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Author*Chao-Hung Lu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chien-Nan Jimmy Liu (National Central Univ., Taiwan)
Pagepp. 792 - 797
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8B-4 (Time: 14:45 - 15:10)
TitleVoltage Island Generation under Performance Requirement for SoC Designs
Author*Wai-Kei Mak, Jr-Wei Chen (National Tsing Hua Univ., Taiwan)
Pagepp. 798 - 803
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8B-5 (Time: 15:10 - 15:35)
TitleFast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Author*Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 804 - 809
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