| Title | Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach |
| Author | *Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong (Tsinghua University, China), Sheldon X.-D. Tan (University of California, Riverside, United States) |
| Page | pp. 751 - 756 |
| Keyword | Power/Ground, Optimization, Random Walk, Leakage |
| Abstract | This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified random walk process to partition the circuit. Then, by utilizing the isolation property of decaps, this new method avoids solving the large nonlinear programming problem in traditional decap optimization process. Also, this method integrates leakage currents optimization algorithm using a refined leakage model. Experimental results demonstrate that our proposed method achieves approximate a 10X speed up over the heuristic method based on sensitivity and only about 6% decap area deviation from the optimal budget using the programming method. |
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| Title | Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks |
| Author | *Sanjay Pant, David Blaauw (University of Michigan, United States) |
| Page | pp. 757 - 762 |
| Keyword | decap, Ldidt, power grid, timing |
| Abstract | Power supply noise increases the circuit delay, which may lead to performance failure of the design. Decoupling capacitance (decap) addition is effective in reducing the power supply noise, thus making the supply network more robust in presence of large switching currents. Traditionally, decaps have been allocated in order to minimize the worst-case voltage drop in the power grid. In this paper, we propose an approach for timing aware decap allocation which uses global time slacks to drive the decap optimization. Non-critical gates with larger timing slacks can tolerate a relatively higher supply voltage drop as compared to the gates on the critical paths. The decap allocation is formulated as a non-linear optimization problem using Lagrangian relaxation and modified adjoint method is used to efficiently obtain the sensitivities of objective function to decap sizes. A fast path-based heuristic is also implemented and compared with the global optimization formulation. The approaches have been implemented and tested on ISCAS85 benchmark circuits and grids of different sizes. Compared to uniformly allocated decaps, the proposed approach utilizes 35.5% less total decap to meet the same delay target. For the same total decap budget, the proposed approach is shown to improve the circuit delay by 10.1% on an average. |
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| Title | A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms |
| Author | Hanif Fatemi, Shahin Nazarian, *Massoud Pedram (University of Southern California, United States) |
| Page | pp. 774 - 779 |
| Keyword | Current-based Method, Short Circuit Power, Noisy input, Crosstalk |
| Abstract | An accurate model is presented in this paper to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage values. Therefore the actual shape of the voltage signal waveforms at the input and output of the cell should be considered in order to precisely calculate the short circuit energy. Previous approaches such as the approximation of the crosstalk induced noisy waveforms with saturated ramps can lead to short circuit energy estimation errors as high as orders of magnitude for a minimum sized inverter. To resolve this shortcoming, a novel current-based logic cell model is utilized, which constructs the output voltage waveform for a given noisy input waveform. The input and output voltage waveforms are then used to calculate the short circuit current, and hence, short circuit energy dissipation. A characterization process is executed for each logic cell in the standard cell library to model the relevant electrical parameters e.g., the parasitic capacitances and nonlinear current sources. Additionally, our model is capable of calculating the short circuit energy dissipation caused by glitches in VLSI circuits, which in some cases can be a key contributor to the total circuit energy dissipation. Experimental results show an average error of about 1% and a maximum error of about 3% compared to SPICE for different types of logic cells under noisy input waveforms including glitches while the runtime speedup is up to 16000. |
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