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The 12th Asia and South Pacific Design Automation Conference

Session 7C Test Cost Reduction Techniques
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 414+415
Chairs: Sudhakar M. Reddy (Univ. of Iowa, United States), Tomoo Inoue (Hiroshima City Univ., Japan)

7C-1 (Time: 10:15 - 10:40)
TitleShelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Author*Danella Zhao, Unni Chandran (Univ. of Louisiana, Lafayette, United States), Hideo Fujiwara (NAIST, Japan)
Pagepp. 714 - 719
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7C-2 (Time: 10:40 - 11:05)
TitleCore-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Author*Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST, Japan), Alex Orailoglu (Univ. of California, San Diego, United States), Hideo Fujiwara (NAIST, Japan)
Pagepp. 720 - 725
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7C-3 (Time: 11:05 - 11:30)
TitleAn Architecture for Combined Test Data Compression and Abort-on-Fail Test
Author*Erik Larsson, Jon Persson (Linköpings Universitet, Sweden)
Pagepp. 726 - 731
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7C-4 (Time: 11:30 - 11:55)
TitleRunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
Author*Hao Fang, Chenguang Tong, Xu Cheng (Peking Univ., China)
Pagepp. 732 - 737
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7C-5 (Time: 11:55 - 12:20)
TitleSystematic Scan Reconfiguration
Author*Ahmad Al-Yamani (KFUPM, Saudi Arabia), Narendra Devta-Prasanna (Univ. of Iowa, United States), Arun Gunda (LSI Logic, United States)
Pagepp. 738 - 743
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