| Title | Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation |
| Author | *Jiayi Liu, Sheqin Dong, Yunchun Ma, Di Long, Xianlong Hong (EDA lab, DCST, Tsinghua University, China) |
| Page | pp. 191 - 196 |
| Keyword | analog layout, symmetry, thermal-driven, CBL representation |
| Abstract | Thermal constraint is very important for analog devices in the context of SOI. Hot-spot effect would cause error or even failure on the performance of analog devices. And the temperature gradient would lead to mismatch on symmetrical devices. In order to handle these problems, this paper introduces an accurate thermal model into the placement process. Based on the geometric symmetry which is achieved with CBL for the first time, the thermal model helps to find the thermal-optimal placement. And the experimental results show this method is promising. |
| PDF file |
| Title | A Graph Reduction Approach to Symbolic Circuit Analysis |
| Author | *Guoyong Shi, Weiwei Chen (Shanghai Jiao Tong University, China), C.-J. Richard Shi (University of Washington, United States) |
| Page | pp. 197 - 202 |
| Keyword | graph, symbolic, BDD, simulator |
| Abstract | A new graph reduction approach to symbolic circuit analysis is developed in this paper.
A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially
designed graph reduction process and a recursive sign determination algorithm.
This combination of techniques is used to develop a core analysis engine of a symbolic analog
circuit simulator that has the potential for analyzing large analog circuits
in the frequency domain. Partial experimental results are reported. |
| PDF file |
| Title | Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic |
| Author | Xuexin Liu, *Wai-Shing Luk, Yu Song, Xuan Zeng (ASIC & System State-Key Lab, Fudan University, China) |
| Page | pp. 203 - 208 |
| Keyword | ellipsoid method, affine arithmetic, geometric programming, robust design |
| Abstract | Analog circuit sizing under process/parameter
variations is formulated as a mini-max geometric programming
problem. To tackle such problem, we present a new method
that combines the ellipsoid method and affine arithmetic. Affine
Arithmetic is not only used for keeping tracks of variations and
correlations, but also helps to determine the sub-gradient at each
iteration of the ellipsoid method. An example of designing a
CMOS op-amp is given to demonstrate the effectiveness of our
method. Finally numerical results are verified by SPICE’s simulation. |
| PDF file |
| Title | WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design |
| Author | *Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng (Fudan University, China) |
| Page | pp. 209 - 214 |
| Keyword | Mixed-signal validation, Waveform comparison, Validation automation |
| Abstract | The increasing effort on full-chip validation constrains design cost and time-to-market. A waveform comparison tool named WCOMP is presented to automate mixed-signal validation regression in memory design. Unlike digital waveform comparison tools, WCOMP compares mixed-signal waveforms for functional match instead of graphical match, which tally with the requirements of full-chip validation regression. Simulations with different regression runs, process parameters, voltages and temperatures can be functionally compared. The methods are proved to be effective in Intel Flash memory design. |
| PDF file |
| Title | Structured Placement with Topological Regularity Evaluation |
| Author | *Shigetoshi Nakatake (University of Kitakyushu, Japan) |
| Page | pp. 215 - 220 |
| Keyword | placement, floorplan, sequence-pair, regular structure, analog layout |
| Abstract | This paper introduces a new concept of floorplanning,
called structured placement.
Regularity is the key criterion
so that the placement can make progress beyond constraint-driven approaches.
We propose a linear time extration of
topological regularity like arrays and rows from a sequence-pair.
Besides, we provide a new simulated annealing (SA) framework,
called dual SA, which optimizes the regularity as an objective function
balancing the size of regular structures against the area efficiency. |
| PDF file |