Design Quality
Design Time Savings
Verification Time Savings
ESE Front-end Features
Graphical entry
of platform
as a netlist of processors, memories, busses and bridges.
Graphical entry
of application
as C/C++ processes communicating over abstract channels.
Graphical mapping
of processes to processors and channels to busses/routes.
Automatic generation
of SystemC TLMs for functional validation.
Automatic generation
of SystemC TLMs for fast, early and accurate timing estimation.
Designer Advantages
Graphical application and platform input:
Freedom from system level design languages
Automatic TLM generation for design decisions:
Easier design space exploration
Functional TLM simulation:
1000x faster simulation than RTL/ISS
Timed TLM annotation:
Early validation of design constraints
Management Benefits
Models are automatically generated:
1000x productivity gain, shorter time to market
Design decisions and models can be exchanged:
Simplified globally-distributed collaboration
Designs can be easily modified and prototyped:
Better market penetration through customization
Models and design decisions can be reused:
Easier derivatives and version management
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CECS
, UC Irvine. All rights reserved.
