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SystemC
Recoding Infrastructure for SystemC v0.6.2 derived from Accellera SystemC 2.3.1
Accellera SystemC proof-of-concept library
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Derived from Accellera SystemC 2.3.1, this library enables Out-of-Order Parallel Discrete Event Simulation (OoO PDES) for SystemC model simulation on multi- and many-core architectures. This software provides the simulator component of the Recoding Infrastructure for SystemC (RISC).
Use this all at your own risk! (Yes, it's a running gag!)
As an integral part of the RISC software, this OoO PDES library is installed together with the other RISC components. Please refer to the RISC installation instructions.
SYSC_PRINT_MODE_MESSAGE can be defined to print the current simulation mode used. SYSC_PAR_SIM_CPUS can be set to the number of CPU cores available for parallel use. SYSC_DISABLE_PREDICTION can be defined to disable prediction optimization during simulation. SYSC_SYNC_PAR_SIM can be defined to force synchronous PDES (no out-of-order execution). SYSC_VERBOSITY_FLAG_1 can be defined to print logging information about thread states. SYSC_VERBOSITY_FLAG_2 can be defined to print logging information about event notifications. SYSC_VERBOSITY_FLAG_3 can be defined to print logging information about waiting threads. SYSC_VERBOSITY_FLAG_4 can be defined to print logging information about what threads an event triggers. SYSC_VERBOSITY_FLAG can be defined to enable all logging information listed above. SYSC_NUM_INVOKERS can be defined to set the number of invoker threads for method processes.Version 0.6.2.
This is an academic proof-of-concept prototype implementation, not commercial-quality software.
Farah Arabi (farabi@uci.edu)
Zhongqi Cheng (zhongqi@uci.edu)
Rainer Doemer (doemer@uci.edu)
Guantao Liu (guantaol@uci.edu)
Daniel Mendoza (dmmendo1@uci.edu)
Tim Schmidt (schmidtt@uci.edu)
1.8.5