risc::Design Class Reference

#include <design.h>

Collaboration diagram for risc::Design:

[legend]

List of all members.

Classes
class	label_writer
class	SegEdge
class	SegNode
Public Types
typedef boost::adjacency_list < boost::vecS, boost::vecS, boost::directedS, SegNode, SegEdge >	graph_t
typedef boost::adjacency_list::vertex_descriptor	VertexDescriptor
Public Member Functions
	Design (int argc, char *argv[], std::vector< std::string > psg_file_names=std::vector< std::string >(0), bool is_psg_mode=false, bool PrintFrontendArgs=false)
	default constructor
	~Design ()
void	initialize_port_mapping ()
void	initialize_interfaces ()
void	initialize_definitions ()
void	initialize_top_modules ()
void	initialize_global_functions ()
void	initialize_global_variables ()
void	initialize_path_instance_mapper ()
void	print_all_class_definitions ()
void	print_all_global_functions ()
void	print_design ()
InstanceTree	get_root ()
Module *	find_module_definition (SgClassDefinition *cd)
PrimitiveChannel *	find_prim_channel_definition (SgClassDefinition *cd)
HierarchicalChannel *	find_channel_definition (SgClassDefinition *cd)
Interface *	find_interface (SgClassDefinition *cd)
Variable *	find_global_variable (SgVariableDefinition *var_def)
	Find a port by it's ast variable definition.
void	reset_instance_counter ()
	This function resets the instance counter of the module and hierarchical channel instances to zero.
bool	perform_static_analysis ()
	The functions return if a static analysis will be performed.
void	add_module_to_definition_list (SgClassDefinition *class_def)
void	add_hierarchical_channel_to_defintion_list (SgClassDefinition *class_def)
std::string	get_design_file_name ()
void	store_port_mapping (std::string)
void	load_port_mapping (std::string)
bool	is_analyzable ()
void	draw_port_mapping ()
Public Attributes
ModuleVector	module_definitions_
InstanceVector	top_modules_
PrimitiveChannelVector	primitive_channel_
HierarchicalChannelVector	hierarchical_channel_
InterfaceVector	interfaces_
VariableVector	global_variables_
FunctionVector	global_functions_
SgProject *	project_
int	old_argc_
char **	old_argv_
std::vector< std::string >	input_files_
std::vector< std::string >	psg_file_names_
PathInstanceMapper *	path_instance_mapper_
PortMappingCache	port_mapping_cache_
std::string	dynamic_analysis_filename_
	This variable contains the filename of the input file for the dynamic analysis.
std::string	instrumentor_output_filename_
	This variable contains the name which will be used for the dir file during the presimulation.
bool	psg_mode
int	psg_count
std::vector< int >	psg_seg_count
std::vector< Thread * >	loaded_threads
	functions that are implemented in the psg but are not simulation processes
std::vector< Thread * >	simulation_threads
ModuleInstanceVector	loaded_module_instances
graph_t	port_mapping_graph
Private Member Functions
	Design (const Design &d)
	Disabled copy constructor.

---

Detailed Description

This class represents the internal representation. The IR offers different interfaces to start search in IR.

---

Member Typedef Documentation

typedef boost::adjacency_list<boost::vecS, boost::vecS, boost::directedS, SegNode, SegEdge> risc::Design::graph_t

typedef boost::adjacency_list ::vertex_descriptor risc::Design::VertexDescriptor

---

Constructor & Destructor Documentation

risc::Design::Design	(	int	argc,
		char *	argv[],
		std::vector< std::string >	psg_file_names = std::vector<std::string>(0),
		bool	is_psg_mode = false,
		bool	PrintFrontendArgs = false
	)			[explicit]

default constructor

Parameters:

	argc	expects argc from main function
	argv	expects argv from main function

risc::Design::~Design

(

)

risc::Design::Design

(

const Design &

d

)

[private]

Disabled copy constructor.

---

Member Function Documentation

void risc::Design::add_hierarchical_channel_to_defintion_list

(

SgClassDefinition *

class_def

)

void risc::Design::add_module_to_definition_list

(

SgClassDefinition *

class_def

)

void risc::Design::draw_port_mapping

(

)

risc::HierarchicalChannel * risc::Design::find_channel_definition

(

SgClassDefinition *

cd

)

risc::Variable * risc::Design::find_global_variable

(

SgVariableDefinition *

var_def

)

Find a port by it's ast variable definition.

risc::Interface * risc::Design::find_interface

(

SgClassDefinition *

cd

)

risc::Module * risc::Design::find_module_definition

(

SgClassDefinition *

cd

)

risc::PrimitiveChannel * risc::Design::find_prim_channel_definition

(

SgClassDefinition *

cd

)

std::string risc::Design::get_design_file_name

(

)

risc::InstanceTree risc::Design::get_root

(

)

void risc::Design::initialize_definitions

(

)

void risc::Design::initialize_global_functions

(

)

void risc::Design::initialize_global_variables

(

)

void risc::Design::initialize_interfaces

(

)

void risc::Design::initialize_path_instance_mapper

(

)

void risc::Design::initialize_port_mapping

(

)

void risc::Design::initialize_top_modules

(

)

bool risc::Design::is_analyzable

(

)

void risc::Design::load_port_mapping

(

std::string

filename

)

function risc::Design::perform_static_analysis

(

)

The functions return if a static analysis will be performed.

void risc::Design::print_all_class_definitions

(

)

void risc::Design::print_all_global_functions

(

)

void risc::Design::print_design

(

)

risc::Design::reset_instance_counter

(

)

This function resets the instance counter of the module and hierarchical channel instances to zero.

void risc::Design::store_port_mapping

(

std::string

filename

)

---

Member Data Documentation

std::string risc::Design::dynamic_analysis_filename_

This variable contains the filename of the input file for the dynamic analysis.

FunctionVector risc::Design::global_functions_

VariableVector risc::Design::global_variables_

HierarchicalChannelVector risc::Design::hierarchical_channel_

std::vector<std::string> risc::Design::input_files_

std::string risc::Design::instrumentor_output_filename_

This variable contains the name which will be used for the dir file during the presimulation.

InterfaceVector risc::Design::interfaces_

ModuleInstanceVector risc::Design::loaded_module_instances

risc::Design::loaded_threads

functions that are implemented in the psg but are not simulation processes

ModuleVector risc::Design::module_definitions_

int risc::Design::old_argc_

char** risc::Design::old_argv_

PathInstanceMapper* risc::Design::path_instance_mapper_

PortMappingCache risc::Design::port_mapping_cache_

graph_t risc::Design::port_mapping_graph

PrimitiveChannelVector risc::Design::primitive_channel_

SgProject* risc::Design::project_

int risc::Design::psg_count

std::vector<std::string> risc::Design::psg_file_names_

bool risc::Design::psg_mode

std::vector<int> risc::Design::psg_seg_count

std::vector<Thread*> risc::Design::simulation_threads

InstanceVector risc::Design::top_modules_

---

The documentation for this class was generated from the following files:

• /local/lecs/lecs/risc_v0.5.0/sources/build/risc_v0.5.0/src/internal_representation/design.h
• /local/lecs/lecs/risc_v0.5.0/sources/build/risc_v0.5.0/src/internal_representation/design.cpp