H.264 HDTV DECODER USING APPLICATION-SPECIFIC NETWORKS-ON-CHIP (WedPmOR3)

Author(s) : Jiang Xu (Princeton University, United States of America) Wayne Wolf (Princeton University, United States of America) Joerg Henkel (University of Karlsruhe, Germany) Srimat Chakradhar (NEC Laboratories America, Inc, United States of America)

Abstract : This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the application-specific networks-on-chip, were used. Regular-topology networks-on-chip (mesh, torus, and fat tree) have been proposed. However, we showed in this paper that the application-specific networks-on-chip provided substantial improvements in power, performance, and cost compared to regular-topology networks-on-chip. We measured the power, performance, area, total switch and link capacity, and switch and link utilization based on floorplans and circuit designs. Measurement results showed that the application-specific networks-on-chip was both faster in absolute terms and more efficient. The application-specific networks-on-chip used 39% less power, 73% less silicon area, 83% less metal area, and 76% less switch capacity and link capacity to achieve 2X performance compared to the RAW network.

Menu