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GLSVLSI 2002 :
[ <A HREF="glsvabs.htm">Abstracts</A> ]
[ <A HREF="glsvsess.htm">Session Index</A> ]
[ <A HREF="glsvai.htm">Author Index</A> ]</H3>
<HR>
<H2>GLSVLSI 2003 TABLE OF CONTENTS</H2>
<B>
Sessions:
[<A HREF="#sess1">1</A>]
[<A HREF="#sess2">2</A>]
[<A HREF="#sess3">3</A>]
[<A HREF="#possess1">Poster Session 1</A>]
[<A HREF="#sess4">4</A>]
[<A HREF="#sess5">5</A>]
[<A HREF="#sess6">6</A>]
[<A HREF="#sess7">7</A>]
[<A HREF="#possess2">Poster Session 2</A>]
[<A HREF="#sess8">8</A>]<P>
<A HREF="../../pdffiles/foreword.pdf">Foreword</A><BR>
<A HREF="../../pdffiles/cfp.pdf">GLSVLSI 2004 Call for Papers</A><BR>
<A HREF="../../pdffiles/symorg.pdf">Symposium Organization</A><P>
</B>
<HR>
<H2>Session 1: <A HREF="glsvabs.htm#sess1" NAME="sess1">
CAD
</A></H2>
<I>
Chair: Jagan Narasimhan
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#1_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s1.1 Constructing Exact Octagonal Steiner Minimal Trees [p. 1]
<DD><I>
C. S. Coulston (Penn State Erie, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#1_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s1.2s Bounding the Efforts on Congestion Optimization for Physical Synthesis [p. 7]
<DD><I>
D. Pandini (STMicroelectronics, USA), L. T. Pileggi, A. J. Strojwas (Carnegie Mellon University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#1_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/1_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s1.3s A Comprehensive High-level Synthesis System for Control-Flow Intensive
Behaviors [p. 11]
<DD><I>
W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong,
N. K. Jha (Princeton University, USA), A. Raghunathan (NEC, USA)
</I><P>
</DL>
<HR>
<H2>Session 2: <A HREF="glsvabs.htm#sess2" NAME="sess2">
VLSI Circuits
</A></H2>
<I>
Chair: Travis Blalock
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#2_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.1 Iterative Decoding In Analog CMOS [p. 15]
<DD><I>
S. Hemati, A. H. Banihashemi (Carleton University, Canada)
</I><P>
<DT>
<A HREF="glsvabs.htm#2_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.2 Design Issues in Low-Voltage High-Speed Current-Mode Logic Buffers [p. 21]
<DD><I>
P. Heydari (University of California, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#2_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.3 Optimum Wire Sizing of RLC Interconnect With Repeaters [p. 27]
<DD><I>
M. A. El-Moursy, E. G. Friedman (University of Rochester, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#2_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.4s Reduced Dynamic Swing Domino Logic [p. 33]
<DD><I>
R. Mader, I. Kourtev (University of Pittsburgh, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#2_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.5s A 5-20 GHz, Low Power FPGA Implemented by SiGe HBT BiCMOS Technology [p. 37]
<DD><I>
C. You, J.-R. Guo, R. P. Kraft, K. Zhou, M. Chu, J. F. McDonald (Rensselaer Polytechnic Institute, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#2_6"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/2_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s2.6s Interconnected Rings and Oscillators as Gigahertz Clock Distribution Nets [p. 41]
<DD><I>
M. S. Maza, M. L. Aranda (INAOE, Mexico)
</I><P>
</DL>
<HR>
<H2>Session 3: <A HREF="glsvabs.htm#sess3" NAME="sess3">
Nanotechnology
</A></H2>
<I>
Chair: Azeez Bhavnagarwala
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#3_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s3.1 Information Storage Capacity of Crossbar Switching Networks [p. 45]
<DD><I>
P. P. Sotiriadis (John Hopkins University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#3_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s3.2 Exploiting Multiple Functionality for Nano-Scale Reconfigurable Systems [p. 50]
<DD><I>
P. Beckett (RMIT University, Australia)
</I><P>
<DT>
<A HREF="glsvabs.htm#3_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s3.3s A 0.07 µm CMOs Flash Analog-to-Digital Converter for High Speed
and Low Voltage Applications [p. 56]
<DD><I>
J. Yoo, K. Choi, J. Ghaznavi (Pennsylvania State University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#3_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/3_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s3.4s Modeling QCA for Area Minimization in Logic Synthesis [p. 60]
<DD><I>
N. Gergel, S. Craft, J. Lach (University of Virginia, USA)
</I><P>
</DL>
<HR>
<H2><A HREF="glsvabs.htm#possess1" NAME="possess1">
Poster Session 1
</A></H2>
<I>
Chair : Ankur Srivastava
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#p1_01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.1 Power-aware Pipelined Multiplier Design Based On 2-Dimentional
Pipeline Gating [p. 64]
<DD><I>
J. Di, J. S. Yuan (University of Central Florida, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.2 Low Power VLSI Sequential Circuit Architecture Using Critical Race Control [p. 68]
<DD><I>
M. Lowy, N. Butler, R. Tinkler (BAE Systems, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.3 A Hybrid Adiabatic Content Addressable Memory for Ultra
Low-Power Applications [p. 72]
<DD><I>
A. Natarajan, D. Jasinski, W. Burleson, R. Tessier (University of Massachusetts, Amherst, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.4 TEM-Cell and Surface Scan to Identify the Electromagnetic Emission
of Integrated Circuits [p. 76]
<DD><I>
T. Ostermann (University of Linz, Austria), B. Deutschmann (austriamicrosystems AG, Austria)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.5 MuTaTe: An Efficient Design for Testability Technique for Multiplexor
based Circuits [p. 80]
<DD><I>
R. Drechsler, J. Shi, G. Fey (University of Bremen, Germany)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.6 Cooling of Integrated Circuits Using Droplet-Based Microfluidics [p. 84]
<DD><I>
V. K. Pamula, K. Chakrabarty (Duke University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.7 Language Emptiness Checking using MDGs [p. 88]
<DD><I>
F. Wang, S. Tahar (Concordia University, Canada)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.8 A System-Level Methodology for Fast Multi-Objective Design
Space Exploration [p. 92]
<DD><I>
G. Palermo, C. Silvano, S. Valsecchi, V. Zaccaria (Politecnico di Milano, Italy)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.9 A Practical CAD Technique for Reducing Power/ground Noise in DSM Circuits [p. 96]
<DD><I>
A. Mukherjee, K. R. Dusety, R. Sankaranarayan (The University of North Carolina at Charlotte, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.10 RF CMOS Circuit Optimizing Procedure and Synthesis Tool [p. 100]
<DD><I>
C. Rajagopal, K. Sridhar, A. Nunez (Syracuse University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.11 Wirelength Reduction by Using Diagonal Wire [p. 104]
<DD><I>
C. Chiang, Q. Su (Synopsys, Inc., USA), C.-S. Chiang (Soochow University, Taiwan)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.12 A Fast Simulation Approach for Inductive Effects of VLSI Interconnects [p. 108]
<DD><I>
X. Qi, G. Leonhardt, D. Flees, X.-D. Yang, S. Kim, S. Mueller, H. Mau (Sun Microsystems, Inc. USA),
L. T. Pileggi (Carnegie Mellon University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_13.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.13 Buffer Sizing for Minimum Energy-Delay Product by Using
an Approximating Polynomial [p. 112]
<DD><I>
C. W. Kang, S. Abbaspour, M. Pedram (University of Southern California, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_14.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.14 FORCE: A Fast and Easy-To-Implement Variable-Ordering Heuristic [p. 116]
<DD><I>
F. A. Aloul, I. L. Markov, K. A. Sakallah (University of Michigan, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.15 Routing Methodology for Minimizing Interconnect Energy Dissipation [p. 120]
<DD><I>
A. Sakai, T. Yamada, Y. Matsushita (SANYO Electric Co., Ltd., Japan),
H. Yasuura (Kyusyu University)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_16"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_16.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.16 Circuit Design of a Wide Tuning Range CMOS VCO with Automatic Amplitude
Control [p. 124]
<DD><I>
J. Chen, B. Shi (Tsinghua University, China)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.17 A Decoupling Technique for CMOS Strong-Coupled Structures [p. 128]
<DD><I>
L. Yang, J. S. Yuan (University of Central Florida, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p1_18"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_18.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p1.18 A Custom FPGA for the Simulation of Gene Regulatory Networks [p. 132]
<DD><I>
I. Tagkopoulos, C. Zukowski, G. Cavelier, D. Anastassiou (Columbia University, USA)
</I><P>
</DL>
<HR>
<H2>Session 4: <A HREF="glsvabs.htm#sess4" NAME="sess4">
VLSI Design
</A></H2>
<I>
Chair: John Lach
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#4_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.1 A Novel Architecture for Power Maskable Arithmetic Units [p. 136]
<DD><I>
L. Benini (Universitˆ di Bologna), A. Macii, E. Macii (Politecnico di Torino, Italy),
E. Omerbegovic (BullDAST s.r.l., Italy), M. Poncino (Universitˆ di Verona, Italy),
F. Pro (BullDAST s.r.l., Italy)
</I><P>
<DT>
<A HREF="glsvabs.htm#4_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.2 3D Direct Vertical Interconnect Microprocessors Test Vehicle [p. 141]
<DD><I>
J. Mayega, O. Erdogan, P. M. Belemjian, K. Zhou, J. F. McDonald, Russel P. Kraft
(Rensselaer Polytechnic Institute, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#4_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.3 Zero Overhead Watermaking Technique for FPGA Designs [p. 147]
<DD><I>
A. K. Jain, L. Yuan, P. R. Pari, G. Qu (University of Maryland, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#4_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.4s Matrix Datapath Architecture for an Iterative 4x4 MIMO Noise
Whitening Algoithm [p. 153]
<DD><I>
G. Knagge (University of Newcastle, Australia),
D. Garrett, S. Venkatesan, C. Nicol (Lucent Technologies, Australia)
</I><P>
<DT>
<A HREF="glsvabs.htm#4_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.5s System Level Design of Real Time Face Recognition Architecture Based
on Composite PCA [p. 157]
<DD><I>
R. Gottumukkal, V. K. Asari (Old Dominion University)
</I><P>
<DT>
<A HREF="glsvabs.htm#4_6"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/4_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s4.6s Design and Modeling of a 16-bit 1.5MSPS Successive Approximation ADC
with Non-binary Capacitor Array [p. 161]
<DD><I>
J. Gan (Cirrus Logic, Inc., USA), S. Yan, J. Abraham (University of Texas at Austin, USA)
</I><P>
</DL>
<HR>
<H2>Session 5: <A HREF="glsvabs.htm#sess5" NAME="sess5">
VLSI Circuits
</A></H2>
<I>
Chair: Ruchir Puri
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#5_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s5.1 Shielding Effect of On-Chip Interconnect Inductance [p. 165]
<DD><I>
M. A. El-Moursy, E. G. Friedman (University of Rochester, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#5_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s5.2 A Pipelined Clock-Delay Domino Carry-Lookahead Adder [p. 171]
<DD><I>
B. A. Shinkre, J. E. Stine (Illinois Institute of Technology, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#5_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s5.3 A Globally Asynchronous Locally Dynamic System for ASICs and SoCs [p. 176]
<DD><I>
A. Chattopadhyay, Z. Zilic (McGill University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#5_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/5_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s5.4s 40 MHz 0.25 µm CMOS Embedded 1T Bit-Line Decoupled DRAM FIFO
for Mixed-Signal Applications [p. 182]
<DD><I>
M. I. Fuller, J. P. Mabry, J. A. Hossack, T. N. Blalock (University of Virginia, USA)
</I><P>
</DL>
<HR>
<H2>Session 6: <A HREF="glsvabs.htm#sess6" NAME="sess6">
CAD
</A></H2>
<I>
Chair: Rhett Davis
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#6_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.1 Design Topology Aware Physical Metrics for Placement Analysis [p. 186]
<DD><I>
S. Ramji, N. R. Dhanwada (IBM Microelectronics, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#6_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.2 A Novel Ultra-Fast Heuristic for VLSI CAD Steiner Trees [p. 192]
<DD><I>
B. Krishna (Intel Corporation, USA), C. Y. R. Chen (Syracuse University, USA),
N. K. Sehgal (Intel Corporation, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#6_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.3 Combining Wire Swapping and Spacing for Low-Power
Deep-Submicron Buses [p. 198]
<DD><I>
E. Macii (Politecnico di Torino, Italy), M. Poncino (Universitˆ di Verona, Italy),
S. Salerno (Politecnico di Torino, Italy)
</I><P>
<DT>
<A HREF="glsvabs.htm#6_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.4s Clustering Based Acyclic Multi-way Partitioning [p. 203]
<DD><I>
E. S. H. Wong, E. F. Y. Young (The Chinese University of H. K.),
W. K. Mak (University of S. Florida, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#6_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.5s Synthesis of Continuous-Time Filters and Analog to Digital Converters
by Integrated Constraint Transformation, Floorplanning and Routing [p. 207]
<DD><I>
H. Tang, H. Zhang, A. Doboli (SUNY-Stony Brook, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#6_6"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/6_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s6.6s Congestion Reduction in Traditional and New Routing Architectures [p. 211]
<DD><I>
A. R. Agnihotri, P. H. Madden (State University of New York at Binghamton, USA)
</I><P>
</DL>
<HR>
<H2>Session 7: <A HREF="glsvabs.htm#sess7" NAME="sess7">
Low Power
</A></H2>
<I>
Chair: Gang Qu
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#7_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s7.1 Simultaneous Peak and Average Power Minimization
during Datapath Scheduling for DSP Processors [p. 215]
<DD><I>
S. P. Mohanty, N. Ranganathan, S. K. Chappidi (University of South Florida, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#7_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s7.2s Unification of Basic Retiming and Supply Voltage Scaling to Minimize Dynamic
Power Consumption for Synchronous Digital Designs [p. 221]
<DD><I>
N. Chabini (Princeton University, USA), E. M. Aboulhamid (UniversitŽ de MontrŽal, Canada),
I. Chabini (Massachusetts Institute of Technology, USA),
Y. Savaria (ƒcole Polytechnique de MontrŽal, Canada)
</I><P>
<DT>
<A HREF="glsvabs.htm#7_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/7_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s7.3s Branch Prediction Techniques for Low-Power VLIW Processors [p. 225]
<DD><I>
G. Palermo (Politecnico di Milano, Italy, STMicroelectronics, Italy), M. Sami, C. Silvano, V. Zaccaria
(Politecnico di Milano, Italy), R. Zafalon (STMicroelectronics, Italy)
</I><P>
</DL>
<HR>
<H2><A HREF="glsvabs.htm#possess2" NAME="possess2">
Poster Session 2
</A></H2>
<I>
Chair: TBA
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#p2_01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.1 Orthogonal Code Generator for 3G Wireless Transceivers [p. 229]
<DD><I>
B. D. Andreev, E. L. Titlebaum, E. G. Friedman (University of Rochester, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.2 54x54-bit Radix-4 Multiplier based on Modified Booth Algorithm [p. 233]
<DD><I>
K. Cho, J. Park, J. Hong, G. Choi (Samsung Electronics Co., Korea)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.3 Power-Time Flexible Architecture For GF(2k) Elliptic Curve Cryptosystem
Computation [p. 237]
<DD><I>
A. A.-A. Gutub, M. K. Ibrahim (King Fahd University of Petroleum and Minerals, Saudi Arabia)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.4 A Novel 32-bit Scalable Multiplier Architecture [p. 241]
<DD><I>
Y. Kolla (Sun Microsystems, Inc. USA), Y.-B. Kim (Northeastern University, USA),
J. Carter (University of Utah, USA),
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.5 High Throughout Overlapped Message Passing for Low Density
Parity Check Codes [p. 245]
<DD><I>
Y. Chen, K. K. Parhi (University of Minnesota, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.6 Exponential Split Accumulator for High-Speed Reduced Area
Low-Power Direct Digital Frequency Synthesizers [p. 249]
<DD><I>
E. Merlo, K-H. Baek, M. J. Choe (Rockwell Scientific Company)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.7 Using Dynamic Domino Circuits in Self-Timed Systems [p. 253]
<DD><I>
J.-L. Yang, E. Brunvand (University of Utah, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.8 Dynamic Single-rail Self-timed Logic Structures for Power
Efficient Synchronous Pipelined Designs [p. 257]
<DD><I>
F. Grassert, D. Timmermann (University of Rostock, Germany)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.9 Comparison of Noise Tolerant Precharge (NTP) to Conventional
Feedback Keepers for Dynamic Logic [p. 261]
<DD><I>
D. Harris, G. Breed, M. Erler, D. Diaz (Harvey Mudd College, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.10 Variable Gain Amplifier with Offset Cancellation [p. 265]
<DD><I>
A. Emira, E. S‡nchez-Sinencio (Texas A&M University, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.11 Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects [p. 269]
<DD><I>
A. Maheshwari, W. Burleson (University of Massachusetts, Amherst, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.12 A Slew Rate Enhancement Technique for Operational Amplifiers
based on a Tunable Active Gm-based Capacitance Multiplication Circuit [p. 273]
<DD><I>
R. Suryanarayan, A. Gupta, T. N. Blalock (University of Virginia, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_13.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.13 A Dual band CMOs VCO with a Balanced Duty Buffer [p. 277]
<DD><I>
Y. C. Han (Samsung Electronics Co., Korea), K. Kim, J. Kim,
K. S. Yoon, J. Chen, B. Shi (Inha University, Korea)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_14.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.14 New Approach to CMOS Current Reference with Very Low
Temperature Coefficient [p. 281]
<DD><I>
J. Chen, B. Shi (Tsinghua University, China)
</I><P>
<DT>
<A HREF="glsvabs.htm#p2_15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
p2.15 Noise Tolerant Low Voltage XOR-XNOR for Fast Arithmetic [p. 285]
<DD><I>
M. Elgamel, S. Goel, M. Bayoumi (University of Louisiana at Lafayette, USA)
</I><P>
</DL>
<HR>
<H2>Session 8: <A HREF="glsvabs.htm#sess8" NAME="sess8">
Testing
</A></H2>
<I>
Chair: TBA
</I>
<DL>
<DT>
<A HREF="glsvabs.htm#8_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s8.1 On Automatic Generation of RTL Validation Test Benches
Using Circuit Testing Techniques [p. 289]
<DD><I>
I. Ghosh (Fujitsu Laboratories of America, USA), S. Ravi (NEC Laboratories of America, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#8_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s8.2s A Highly Regular Multi-Phase Reseeding Technique for Scan-based BIST [p. 295]
<DD><I>
E. Kalligeros, X. Kavousianos (University of Patras, Greece),
D. Nikolos (Computer Technology Institute, Greece)
</I><P>
<DT>
<A HREF="glsvabs.htm#8_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s8.3s Coefficient-Based Parametric Faults Detection in Analog Circuits [p. 299]
<DD><I>
Z. Guo (New Jersey Institute of Technology, USA)
</I><P>
<DT>
<A HREF="glsvabs.htm#8_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/8_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
s8.4s Mixing ATPG and Property Checking for Testing HW/SW Interfaces [p. 303]
<DD><I>
A. Fin, F. Fummi, G. Pravadelli (University of Verona, Italy)
</I><P>
</DL>
]]>