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ISLPED'99 :
[ <A HREF="lpedabs.htm">Abstracts</A> ]
[ <A HREF="lpedsess.htm">Session Index</A> ]
[ <A HREF="lpedai.htm">Author Index</A> ]</H3>
<HR>
<H2>ISLPED'99 TABLE OF CONTENTS </H2>
<B>
Sessions:
[<A HREF="#keynote1">Keynote Session 1</A>]
[<A HREF="#sessk11">K1.1</A>]
[<A HREF="#sessk12">K1.2</A>]
[<A HREF="#sesss1">S1</A>]
[<A HREF="#sesss2">S2</A>]
[<A HREF="#sesss3">S3</A>]
[<A HREF="#sesss4">S4</A>]
[<A HREF="#sessp1">P1</A>]
[<A HREF="#sessp2">P2</A>]
[<A HREF="#sesss5">S5</A>]
[<A HREF="#sesss6">S6</A>]
[<A HREF="#panel">Panel</A>]
[<A HREF="#keynote2">Keynote Session 2</A>]
[<A HREF="#sessk21">K2.1</A>]
[<A HREF="#sessk22">K2.2</A>]
[<A HREF="#sesss7">S7</A>]
[<A HREF="#sesss8">S8</A>]
[<A HREF="#sesss9">S9</A>]
[<A HREF="#sesss10">S10</A>]
[<A HREF="#sessp3">P3</A>]
[<A HREF="#sessp4">P4</A>]
</P>
<A HREF="../../pdffiles/welcome.pdf">Welcome</A><BR>
<A HREF="../../pdffiles/comm.pdf">Committees</A><BR>
<A HREF="../../pdffiles/rev.pdf">Reviewers</A><P>
</B>
<HR>
<H2>
<A NAME="keynote1">
Keynote Session 1
</A></H2>
<I>Chair: David Blaauw</I><P>
<HR>
<H2>
<A NAME="sessk11">
Session K1.1
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#k1_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/k1_1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Power RF Integrated Circuits: Principles and Practice [p. 1]
<DD><I>A. A. Abidi, H. Darabi</I><P>
</DL>
<HR>
<H2>
<A NAME="sessk12">
Session K1.2:
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#k1_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/k1_2scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Algorithm and Architecture of a 1V Low Power Hearing Instrument DSP [p. 7]
<DD><I>Finn Meller, Nikolai Bisgaard, John Melanson</I><P>
</DL>
<HR>
<H2>
Session S1:
<A HREF="lpedabs.htm#sesss1" NAME="sesss1">
Low-Power Digital Circuit Techniques
</A></H2>
<I>Chair: Kaushik Roy</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#01_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S1.1 A Shared-Bitline SRAM Cell Architecture for 1-V Ultra Low-Power Word-Bit
Configurable Macrocells
[p. 12]
<DD><I>Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka</I><P>
<DT>
<A HREF="lpedabs.htm#01_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S1.2 Retractile Clock-Powered Logic [p. 18]
<DD><I>Nestoras Tzartzanis, William Athas</I><P>
<DT>
<A HREF="lpedabs.htm#01_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S1.3 Energy-Efficient Dynamic Circuit Design in the Presence of Crosstalk Noise
[p. 24]
<DD><I>Ganesh Balamurugan, Naresh R. Shanbhag</I><P>
</DL>
<HR>
<H2>Session S2:
<A HREF="lpedabs.htm#sesss2" NAME="sesss2">
Signal Processing Architecture
</A></H2>
<I>Chair: Naresh Shanbhag</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#02_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S2.1 Energy-Efficient Signal Processing via Algorithmic Noise-Tolerance
[p. 30]
<DD><I>Rajamohana Hegde, Naresh R. Shanbhag</I><P>
<DT>
<A HREF="lpedabs.htm#02_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S2.2 Reducing Power Consumption of Turbo Code Decoder Using Adaptive Iteration
With Variable Supply Voltage
[p. 36]
<DD><I>Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-ying Tsui, Roger S. Cheng</I><P>
<DT>
<A HREF="lpedabs.htm#02_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S2.3 A Low Energy Architecture for Fast PN Acquisition [p. 42]
<DD><I>Christopher Deng, Charles Chien</I><P>
</DL>
<HR>
<H2>Session S3:
<A HREF="lpedabs.htm#sesss3" NAME="sesss3">
Power Management and Low Voltage
</A></H2>
<I>Chair: Rick Carley<BR>
</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#03_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S3.1 Vibration-to-Electric Energy Conversion [p. 48]
<DD><I>Scott Meninger, Jose Oscar Mur-Miranda, Rajeevan Amirtharajah,
Anantha Chandrakasan, Jeffrey Lang</I><P>
<DT>
<A HREF="lpedabs.htm#03_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_2scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S3.2 Variable Supply-Voltage Scheme with 95%-Efficiency DC-DC Converter for
MPEG-4 Codec [p. 54]
<DD><I>Fuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru
Furuyama</I><P>
<DT>
<A HREF="lpedabs.htm#03_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S3.3 Circuit Methods for the Integration of Low Voltage (1.1-1.8V) Analog
Functions on System-on-a-Chip IC's in a Single-Poly CMOS Processes [p. 60]
<DD><I>Vladimir Koifman, Yachin Afek, Joseph Shor</I><P>
</DL>
<HR>
<H2>Session S4:
<A HREF="lpedabs.htm#sesss4" NAME="sesss4">
Cache/Memory Systems
</A></H2>
<I>Chair: Christian Piguet</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#04_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S4.1 Using Dynamic Cache Management Techniques to Reduce Energy in a
High-Performance Processor
[p. 64]
<DD><I>Nikolaos Bellas, Ibrahim Hajj, Constantine Polychronopoulos</I><P>
<DT>
<A HREF="lpedabs.htm#04_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S4.2 Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple
Line Buffers and Bit-Line Segmentation[p. 70]
<DD><I>Kanad Ghose, Milind B. Kamble</I><P>
<DT>
<A HREF="lpedabs.htm#04_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S4.3 Energy Efficient Data Transfer and Storage Organization for a MAP
Turbo Decoder Module
[p. 76]
<DD><I>Curt Schurgers, Francky Catthoor, Marc Engels</I><P>
</DL>
<HR>
<H2>Session P1:
<A HREF="lpedabs.htm#sessp1" NAME="sessp1">
Low Power Circuits
</A></H2>
<I>Chair: Barton Brock</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#p1_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.1 Mixed-Swing QuadRail for Low Power Dual-Rail Domino Logic [p. 82]
<DD><I>Bharath Ramasubramanian, Herman Schmit, L. Richard Carley</I><P>
<DT>
<A HREF="lpedabs.htm#p1_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.2 Databus Charge Recovery: Practical Considerations
[p. 85]
<DD><I>Benjamin Bishop, Mary Jane Irwin </I><P>
<DT>
<A HREF="lpedabs.htm#p1_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.3 SC<SUP>2</SUP>L; A Low-Power High-Performance Dynamic Differential Logic
Family[p. 88]
<DD><I>Amr M. Fahim, Mohamed I. Elmasry
</I><P>
<DT>
<A HREF="lpedabs.htm#p1_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.4 Conforming Inverted Data Store for Low Power Memory
[p. 91]
<DD><I>You-Sung Chang, Bong-II Park, Chong-Min Kyung</I><P>
<DT>
<A HREF="lpedabs.htm#p1_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.5 Ultra-Low Power Digital Subthreshold Logic Circuits [p. 94]
<DD><I>Hendrawan Soeleman, Kaushik Roy</I><P>
<DT>
<A HREF="lpedabs.htm#p1_6"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p1_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P1.6 Single-Phase Source-Coupled Adiabatic Logic [p. 97]
<DD><I>Suhwan Kim, Marios C. Papaefthymiou</I><P>
</DL>
<HR>
<H2>Session P2:
<A HREF="lpedabs.htm#sessp2" NAME="sessp2">
System & Analog Low Power Design
</A></H2>
<I>Chair: Enrico Macii</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#p2_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P2.1 Global Register Allocation for Minimizing Energy Consumption
[p. 100]
<DD><I>Yumin Zhang, Xiaobo (Sharon) Hu, Danny Z. Chen</I><P>
<DT>
<A HREF="lpedabs.htm#p2_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P2.2 Power Macro-Models for DSP Blocks with Application to High-Level Synthesis
[p. 103]
<DD><I>Subodh Gupta, Farid N. Najm</I><P>
<DT>
<A HREF="lpedabs.htm#p2_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P2.3 Power Minimization of High-Performance Submicron CMOS Circuits Using a
Dual-V<SUB>dd</SUB> Dual-V<SUB>th</SUB> (DVDV) Approach [p. 106]
<DD><I>Muhammad M. Khellah, K.I. Elmasry</I><P>
<DT>
<A HREF="lpedabs.htm#p2_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P2.4 A Completely On-Chip Voltage Regulation Technique for Low Power Digital
Circuits [p. 109]
<DD><I>L. Richard Carley, Akshay Aggarwal</I><P>
<DT>
<A HREF="lpedabs.htm#p2_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p2_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P2.5 Comparison of Class A Amplifiers for Low-Power and Low-Voltage Switched
Capacitor Applications [p. 112]
<DD><I>Christoph Schwoerer, Dominique Morche, Patrice Senn</I><P>
</DL>
<HR>
<H2>Session S5:
<A HREF="lpedabs.htm#sesss5" NAME="sesss5">
Power Estimation
</A></H2>
<I>Chair: Rajendran Panda</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#05_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S5.1 Lower and Upper Bounds on the Switching Activity in Scheduled Data Flow
Graphs [p. 115]
<DD><I>Lars Kruse, Eike Schmidt, Gerd Jochens, Wolfgang Nebel</I><P>
<DT>
<A HREF="lpedabs.htm#05_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S5.2 Energy-Per-Cycle Estimation at RTL [p. 121]
<DD><I>Subodh Gupta, Farid N. Najm</I><P>
<DT>
<A HREF="lpedabs.htm#05_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S5.3 Efficient Switching Activity Computation During High-Level Sythesis of
Control-Dominated Designs [p. 127]
<DD><I>A. Bogliolo, L. Benini, B. Riccó, G. De Micheli</I><P>
<DT>
<A HREF="lpedabs.htm#05_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S5.4 Non-Stationary Effects in Trace-Driven Power Analysis [p. 133]
<DD><I>Radu Marculescu, Diana Marculescu, Massoud Pedram</I><P>
</DL>
<HR>
<H2>Session S6:
<A HREF="lpedabs.htm#sesss6" NAME="sesss6">
Circuit-Level Low-Power Design Techniques
</A></H2>
<I>Chair: George Stamoulis
</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#06_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S6.1 Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits [p. 139]
<DD><I>Vijay Sundararajan, Keshab K. Parhi</I><P>
<DT>
<A HREF="lpedabs.htm#06_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S6.2 Clock Distribution Using Multiple Voltages
[p. 145]
<DD><I>Jatuchai Pangjun, Sachin S. Sapatnekar </I><P>
<DT>
<A HREF="lpedabs.htm#06_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S6.3 Monotonic Static CMOS and Dual V<SUB>T</SUB> Technology [p. 151]
<DD><I>Tyler Thorp, Gin Yee, Carl Sechen</I><P>
<DT>
<A HREF="lpedabs.htm#06_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S6.4 VIP - An Input Pattern Generator for Identifying Critical Voltage Drop for
Deep Sub-Micron Designs [p. 156]
<DD><I>Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng </I><P>
</DL>
<HR>
<A NAME="panel">
<H2>Evening Panel:<P>
</A>
<A HREF="../../pdffiles/panel.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
From Devices to Systems : Re-Directing the Future of Low Power Design [p. 162]
</H2>
<I>Moderator: Massoud Pedram <BR>
Panelists : William C. Athas, Edmund K. Cheng, Robert P. Colwell,
William P. Kaiser, Jose Munoz, Saed Younis</I><P>
</DL>
<HR>
<H2>
<A NAME="keynote2">
Keynote Session 2
</A></H2>
<I>Chair: Jason Cong</I><P>
<HR>
<H2>
<A HREF="lpedabs.htm#sessk21" NAME="sessk21">
Session K2.1
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#k2_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/k2_1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Technology and Design Challenges for Low Power and High Performance
[p. 163]
<DD><I>Vivek De, Shekhar Borkar</I><P>
</DL>
<HR>
<H2>
<A HREF="lpedabs.htm#sessk22" NAME="sessk22">
Session K2.2
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#k2_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/k2_2scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Advanced Battery Systems: Chemistry, Construction and Characteristics
[p. 169]
<DD><I>Subbarao Surampudi</I><P>
</DL>
<HR>
<H2>Session S7:
<A HREF="lpedabs.htm#sesss7" NAME="sesss7">
Digital Logic and Arithmetic
</A></H2>
<I>Chair: John Arends</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#07_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S7.1 Power Scalable Processing Using Distributed Arithmetic [p. 170]
<DD><I>Rajeevan Amirtharajah, Thucydides Xanthopoulos, Anantha Chandrakasan</I><P>
<DT>
<A HREF="lpedabs.htm#07_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S7.2 Challenges in Clockgating in a Low Power ASIC Methodology [p. 176]
<DD><I>David Garrett, Mircea Stan, Alvar Dean</I><P>
<DT>
<A HREF="lpedabs.htm#07_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S7.3 Modeling and Automating Selection of Guarding Techniques for Datapath
Elements [p. 182]
<DD><I>William E. Dougherty, Donald E. Thomas</I><P>
<DT>
<A HREF="lpedabs.htm#07_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S7.4 The Design of a Low Energy FPGA [p. 188]
<DD><I>Varghese George, Hui Zhang, Jan M. Rabaey</I><P>
</DL>
<HR>
<H2>Session S8:
<A HREF="lpedabs.htm#sesss8" NAME="sesss8">
Power Aware System Design
</A></H2>
<I>Chair: Diana Marculescu</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#08_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S8.1 Stochastic Modeling of a Power-Managed System: Construction and Optimization [p. 194]
<DD><I>Qinru Qiu, Qing Wu, Massoud Pedram</I><P>
<DT>
<A HREF="lpedabs.htm#08_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S8.2 The Impact of Battery Capacity and Memory Bandwidth on CPU Speed-Setting:
A Case Study [p. 200]
<DD><I>Thomas L. Martin, Daniel P. Siewiorek</I><P>
<DT>
<A HREF="lpedabs.htm#08_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S8.3 Selective Instruction Compression for Memory Energy Reduction in
Embedded Systems [p. 206]
<DD><I>Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino</I><P>
<DT>
<A HREF="lpedabs.htm#08_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S8.4 Energy-Efficient Design of Battery-Powered Embedded Systems [p. 212]
<DD><I>Tajana Simunic, Luca Benini, Giovanni De Micheli</I><P>
</DL>
<HR>
<H2>Session S9:
<A HREF="lpedabs.htm#sesss9" NAME="sesss9">
Low Voltage Technology and Modeling
</A></H2>
<I>Chair: Jim Burn</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#09_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S9.1 A Physical Alpha-Power Law MOSFET Model [p. 218]
<DD><I>Keith A. Bowman, Blanca L. Austin, John C. Eble, Xinghai Tang,
James D. Meindl</I><P>
<DT>
<A HREF="lpedabs.htm#09_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S9.2 Hysteresis Effect in Floating-Body Partially-Depleted SOI CMOS Domino
Circuits [p. 223]
<DD><I>R. Puri, C.T. Chuang</I><P>
<DT>
<A HREF="lpedabs.htm#09_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_3scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S9.3 Impact of Using Adaptive Body Bias to Compensate Die-to-Die Vt Variation
on Within-Die Vt Variation [p. 229]
<DD><I>Siva Narendra, Dimitri Antoniadis, Vivek De</I><P>
</DL>
<HR>
<H2>Session S10:
<A HREF="lpedabs.htm#sesss10" NAME="sesss10">
Integrated Wireless Subsystems
</A></H2>
<I>Chair: Lou Williams</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#10_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S10.1 A 1.2V, 430 MHz, 4dBm Power Amplifier and a 250uW Front-End, Using a
Standard Digital CMOS Process [p. 233]
<DD><I>T. Melly, A.-S. Porret, C.C. Enz, M. Kayal, E. Vittoz</I><P>
<DT>
<A HREF="lpedabs.htm#10_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S10.2 CMOS Front-End LNA-Mixer for Micropower RF Wireless Systems [p. 238]
<DD><I>Razieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser</I><P>
<DT>
<A HREF="lpedabs.htm#10_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
S10.3 Differential PLL for Wireless Applications Using Differential CMOS
LC-VCO and Differential Charge Pump [p. 243]
<DD><I>Ayman ElSayed, Akbar Ali, M.I. Elmasry </I><P>
</DL>
<HR>
<H2>Session P3:
<A HREF="lpedabs.htm#sessp3" NAME="sessp3">
Circuit Design & Optimization
</A></H2>
<I>Chair: Chi-ying Tsui</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#p3_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p3_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.1 Passive Precharge and Rippled Power Logic (PPRPL) [p. 249]
<DD><I>Samuel B. Schaevitz, Christopher Lin</I><P>
<DT>
<A HREF="lpedabs.htm#p3_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p3_2scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.2 Technology Scaling Behavior of Optimum Reverse Body Bias for Standby
Leakage Power Reduction in CMOS IC's [p. 252]
<DD><I>Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkins,
Kaushik Roy, Vivek De</I><P>
<DT>
<A HREF="lpedabs.htm#p3_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p3_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.3 An Architectural Solution for the Inductive Noise Problem due to
Clock-Gating [p. 255]
<DD><I>Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari</I><P>
<DT>
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<A HREF="../../pdffiles/p3_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.4 An Optimization Technique for Dual-Output Domino Logic [p. 258]
<DD><I>Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm</I><P>
<DT>
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<A HREF="../../pdffiles/p3_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.5 Statistically Optimized Asynchronous Barrel Shifters for Variable Length
Codecs [p. 261]
<DD><I>Peter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim</I><P>
<DT>
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<A HREF="../../pdffiles/p3_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P3.6 Inverse Polarity Techniques for High Speed/Low-Power Multipliers [p. 264]
<DD><I>Pascal C.H. Meier, Rob A. Rutenbar, L. Richard Carley </I><P>
</DL>
<HR>
<H2>Session P4:
<A HREF="lpedabs.htm#sessp4" NAME="sessp4">
Architecture & Systems
</A></H2>
<I>Chair: Mahadevamurty Nemani</I><P>
<DL>
<DT>
<A HREF="lpedabs.htm#p4_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p4_1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P4.1 Instruction Fetch Energy Reduction Using Loop Caches for Embedded
Applications With Small Right Loops [p. 267]
<DD><I>Lea Hwang Lee, Bill Moyer, John Arends </I><P>
<DT>
<A HREF="lpedabs.htm#p4_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p4_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P4.2 A Methodology for Power Efficient Partitioning of Data-Dominated Algorithm
Specifications Within Performance Constraints [p. 270]
<DD><I>K. Masselos, K. Danckaert, F. Catthoor, C.E. Goutis, H. DeMan </I><P>
<DT>
<A HREF="lpedabs.htm#p4_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p4_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P4.3 Way-Predicting Set-Associative Cache for High Performance and Low
Energy Consumption [p. 273]
<DD><I>Koji Inoue, Tohru Ishihara, Kazuaki Murakami</I><P>
<DT>
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<A HREF="../../pdffiles/p4_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P4.4 Designing Power Efficient Hypermedia Processors [p. 276]
<DD><I>Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith
</I><P>
<DT>
<A HREF="lpedabs.htm#p4_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p4_5scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
P4.5 Dynamic Power Estimation Using the Probabilistic Contribution Measure
(PCM) [p. 279]
<DD><I>Hoon-Sang Jin, Myung-Soo Jang, Jin-Suk Song, Jin-Yong Lee, Taek-Soo
Kim, Jeong-Taek Kong</I><P>
</DL>
<HR>
<H2>
<A NAME="sesst1">
Tutorial 1:
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#t1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/t1scan.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
T1 Circuit Styles and Strategies for CMOS VLSI Design on SOI
[p. 282]
<DD><I>Fari Assaderaghi</I><P>
</DL>
<HR>
<H2>
<A NAME="sesst2">
Tutorial 2:
</A></H2>
<DL>
<DT>
<A HREF="lpedabs.htm#t2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/t2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
T2 System-Level Power Optimization: Techniques and Tools [p. 288]
<DD><I>Luca Benini, Giovanni De Micheli</I><P>
</DL>
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