<![CDATA[
<body>
<h3><a href="../../../../../main_ss.htm">CDROM Home Page</a><br>
<a href="../../../comp95ss.htm">1995 Compendium Index</a><br>
ASP-DAC 95:
[ <a href="aspabs.htm">Abstracts</a> ]
[ <a href="aspsess.htm">Session Index</a> ]
[ <a href="aspai.htm">Author Index</a> ]</h3>
<hr>
<h2>TABLE OF CONTENTS ASP-DAC '95</h2>
Sessions<br>
<a href="#sess1A">[1A]</a>
<a href="#sess1B">[1B]</a>
<a href="#sess1C">[1C]</a>
<a href="#sess2A">[2A]</a>
<a href="#sess2B">[2B]</a>
<a href="#sess2C">[2C]</a>
<a href="#sess3A">[3A]</a>
<a href="#sess3B">[3B]</a>
<a href="#sess3C">[3C]</a>
<a href="#sess4A">[4A]</a>
<a href="#sess4B">[4B]</a>
<a href="#sess4C">[4C]</a>
<a href="#sess5A">[5A]</a>
<a href="#sess5B">[5B]</a>
<a href="#sess5C">[5C]</a>
<a href="#sess6A">[6A]</a>
<a href="#sess6B">[6B]</a>
<a href="#sess6C">[6C]</a>
<a href="#sess7A">[7A]</a>
<a href="#sess7B">[7B]</a>
<a href="#sess7C">[7C]</a>
<a href="#sess8A">[8A]</a>
<a href="#sess8B">[8B]</a>
<a href="#sess8C">[8C]</a>
<a href="#sess9A">[9A]</a>
<a href="#sess9B">[9B]</a>
<a href="#sess9C">[9C]</a><p>
<a href="../../pdffiles/frontmat.pdf">Advisory Board</a><br>
<a href="../../pdffiles/frontmat.pdf">Organizing Committee</a><br>
<a href="../../pdffiles/frontmat.pdf">Steering Committee</a><br>
<a href="../../pdffiles/frontmat.pdf">General Chair's Message</a><br>
<a href="../../pdffiles/frontmat.pdf">ASP-DAC '95 Program Committee</a><br>
<a href="../../pdffiles/frontmat.pdf">ASP-DAC '95 Program Committee Chair's Message</a><br>
<a href="../../pdffiles/frontmat.pdf">ASP-DAC '95 Best Paper Candidates</a><br>
<a href="../../pdffiles/frontmat.pdf">Keynote Address I - Atsushi Asada</a><br>
<a href="../../pdffiles/frontmat.pdf">Keynote Address II - Jim Meadlock</a><br>
<a href="../../pdffiles/frontmat.pdf">Keynote Address III - John Darringer</a><p>
<hr>
<h3>
Session [A-1A] <a href="aspabs.htm#sess1A" name="sess1A">
Design Methodologies for Low Power
</a></h3>
<i>Chair: Massoud Pedram (Univ. of South California, USA)</i><br>
<i>Co-Chair: Hidetoshi Onodera (Kyoto Univ., Japan)</i><p>
<a href="aspabs.htm#1a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1a_1.pdf" name="1a_1"><img src="../../../pdficon.gif"></a>
<b>A-1A.1 Transistor Reordering Rules for Power Reduction in CMOS Gates
</a><br></b>
<i>Wen-Zen Shen, Jiing-Yuan Lin (National Chiao Tung Univ., Taiwan),
Fong-Wen Wang (Telecommunication Laboratories, MTC, Taiwan)</i><p>
<a href="aspabs.htm#1a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1a_2.pdf" name="1a_2"><img src="../../../pdficon.gif"></a>
<b>A-1A.2 Power Reduction by Gate Sizing with Path-Oriented Slack Calculation
</a><br></b>
<i>How-Rern Lin and TingTing Hwang(Tsing Hua Univ., Taiwan)</i><p>
<a href="aspabs.htm#1a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1a_3.pdf" name="1a_3"><img src="../../../pdficon.gif"></a>
<b>A-1A.3 Current and Charge Estimation in CMOS Circuits
</a><br></b>
<i>Sanjay Dhar, Dave J. Gurney (Mentor Graphics Corp., USA)</i><p>
<hr>
<h3>
Session [A-1B] <a href="aspabs.htm#sess1B" name="sess1B">
Design Methodology for Processor and Telecommunication Systems
</a></h3>
<i>Chair: Winfried Hahn (Univ. of Passau, Germany)</i><br>
<i>Co-Chair: Yoshio Takamine (Hitachi Ltd., Japan)</i><p>
<a href="aspabs.htm#1b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1b_1.pdf" name="1b_1"><img src="../../../pdficon.gif"></a>
<b>A-1B.1 Auriga2: A 4.7 Million-Transistor CISC Microprocessor
</a><br></b>
<i>J. P. Tual, M. Thill, C. Bernard, H. N. Nguyen, F. Mottini, M. Moreau,
P. Vallet (BULL S. A., France)</i><p>
<a href="aspabs.htm#1b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1b_2.pdf" name="1b_2"><img src="../../../pdficon.gif"></a>
<b>A-1B.2 Automatic Design for Bit-Serial MSPA Architecture
</a><br></b>
<i>Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito,
(Tokyo Inst. of Technology, Japan, Saitama University, Saitama)</i><p>
<a href="aspabs.htm#1b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1b_3.pdf" name="1b_3"><img src="../../../pdficon.gif"></a>
<b>A-1B.3 Stoht --- An SDL-to-Hardware Translator
</a><br></b>
<i>Ivanil S. Bonatti, Renato J. O. Figueiredo (Univ. of Campinas, Brazil)</i><p>
<a href="aspabs.htm#1b_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/1b_4.pdf" name="1b_4"><img src="../../../pdficon.gif"></a>
<b>A-1B.4 Enhancing a VHDL Based Design Methodology with Application
Specific Data Abstraction
</a><br></b>
<i>Lars Lindqvist (NKT Electronik A/S and Danmarks Tekniske Univ., Denmark)</i><p>
<hr>
<h3>
Session [A-1C] <a href="../../pdffiles/1c_0.pdf" name="sess1C">
PANEL: Design Automation 2000---Challenges for Gigabit-Era
</a></h3>
Moderator: <i>Richard K. Wallace, Editor-in-Chief, EE Times</i><br>
Panelists: <i>Joseph B. Costello (CEO, Cadence),
Jeffrey H. Edson (VP, Intergraph),
Aart deGeus (CEO, Synopsys),
Alan J. Hanover (CEO, Viewlogic),
Jinya Katsube (VP, Zuken),
Walden C. Rhines (CEO, Mentor)</i><p>
<hr>
<h3>
Session [A-2A] <a href="aspabs.htm#sess2A" name="sess2A">
High Level Synthesis (1)
</a></h3>
<i>Chair: Daniel D. Gajski (Univ. of California at Irvine, USA)</i><br>
<i>Co-Chair: Tadatoshi Ishii (Toshiba Corp., Japan)</i><p>
<a href="aspabs.htm#2a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2a_1.pdf" name="2a_1"><img src="../../../pdficon.gif"></a>
<b>A-2A.1 A Scheduling Algorithm for Synthesis of Bus-Partitioned Architectures
</a><br></b>
<i>Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru (Kyoto Univ., Japan)</i><p>
<a href="aspabs.htm#2a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2a_2.pdf" name="2a_2"><img src="../../../pdficon.gif"></a>
<b>A-2A.2 Reclocking for High-Level Synthesis
</a><br></b>
<i>Pradip Jha, Nikil Dutt (Univ. of California, Irvine, USA), Sri Parameswaran (Univ. of Queensland, Australia) </i><p>
<a href="aspabs.htm#2a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2a_3.pdf" name="2a_3"><img src="../../../pdficon.gif"></a>
<b>A-2A.3 Synthesis of False Loop Free Circuits
</a><br></b>
<i>Shih Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu (Univ. of California, Riverside, USA),
Yen-Jen Oyang (National Taiwan Univ., Taiwan)</i><p>
<a href="aspabs.htm#2a_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2a_4.pdf" name="2a_4"><img src="../../../pdficon.gif"></a>
<b>A-2A.4 High-Level Synthesis Scheduling and Allocation Using Genetic Algorithms
</a><br></b>
<i>M. J. M. Heijligers, L. J. M. Cluitmans, J. A. G. Jess
(Eindhoven Univ. of Technology, The Netherlands)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess2B" name="sess2B">
Session [A-2B]
Design Abstractions and Environments
</a></h3>
<i>Chair: Graham R. Hellestrand (Univ. of New South Wales, Australia)</i><br>
<i>Co-Chair: Masatoshi Sekine (Toshiba Corp., Japan)</i><p>
<a href="aspabs.htm#2b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2b_1.pdf" name="2b_1"><img src="../../../pdficon.gif"></a>
<b>A-2B.1 A Framework for the Analysis and Design of Algorithms for a
Class of VLSI-CAD Optimization Problems
</a><br></b>
<i>C. -J. Shi, (Univ. of Iowa, USA), J. A. Brzozowski (Univ. of Waterloo, Canada)</i><p>
<a href="aspabs.htm#2b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2b_2.pdf" name="2b_2"><img src="../../../pdficon.gif"></a>
<b>A-2B.2 Generic Fuzzy Logic CAD Development Tool
</a><br></b>
<i>Eric Q. Kang, Eugene Shragowitz (Univ. of Minnesota, USA)</i><p>
<a href="aspabs.htm#2b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2b_3.pdf" name="2b_3"><img src="../../../pdficon.gif"></a>
<b>A-2B.3 A Hardware/Software Codesign Method for Pipelined Instruction Set
Processor Using Adaptive Database
</a><br></b>
<i>Nguyen Ngoc Binh, Masaharu Imai, Akichika Shiomi,
(Toyohashi Univ. of Technology, Japan),
Nobuyuki Hikichi, (Software Research Associates, Inc., Japan)</i><p>
<a href="aspabs.htm#2b_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2b_4.pdf" name="2b_4"><img src="../../../pdficon.gif"></a>
<b>A-2B.4 EMPAR: An Interactive Synthesis Environment for Hardware Emulations
</a><br></b>
<i>Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu (Tsing Hua Univ., Taiwan)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess2C" name="sess2C">
Session [A-2C]
<SPECIAL SESSION> System-Level Design Automation Activities in Korea (1)
</a></h3>
<i>Chair: Chong-Min Kyung, KAIST, Korea</i><p>
<a href="aspabs.htm#2c_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2c_1.pdf" name="2c_1"><img src="../../../pdficon.gif"></a>
<b>A-2C.1 A Scheduling Algorithm for Multiport Memory Minimization in Datapath
Synthesis
</a><br></b>
<i>Hae-Dong Lee, Sun-Young Hwang (Sogang Univ., Korea)</i><p>
<a href="aspabs.htm#2c_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2c_2.pdf" name="2c_2"><img src="../../../pdficon.gif"></a>
<b>A-2C.2 An Integrated Hardware-Software Cosimulation Environment
for Heterogeneous Systems Prototyping
</a><br></b>
<i>Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn,
Wonyong Sung, Kiyoung Choi, Soonhoi Ha (Seoul National Univ., Korea)</i><p>
<a href="aspabs.htm#2c_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2c_3.pdf" name="2c_3"><img src="../../../pdficon.gif"></a>
<b>A-2C.3 A CSIC Implementation with POCSAG Decoder and Microcontroller
for Paging Applications
</a><br></b>
<i>J.Y. Lim , G. Kim (PANTECH Co., Ltd., Korea), I.S. O (Univ. of Inchon, Korea),
J.H. Cho, Y.J. Kim, H.Y. Kim (PANTECH Co., Ltd., Korea)</i><p>
<a href="aspabs.htm#2c_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/2c_4.pdf" name="2c_4"><img src="../../../pdficon.gif"></a>
<b>A-2C.4 Performance-Driven Circuit Partitioning for Prototyping by
Using Multiple FPGA Chips
</a><br></b>
<i>Chunghee Kim, Hyunchul Shin (Hanyang Univ., Korea),
Younguk Yu (Seodu Logic Inc., Korea)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess3A" name="sess3A">
Session [A-3A]
Partition and Floorplan
</a></h3>
<i>Chair: Chung-Kuan Cheng (Univ. of California, San Diego, USA)</i><br>
<i>Co-Chair: Kazuhiro Ueda (Shibaura Inst. of Technology, Japan)</i><p>
<a href="aspabs.htm#3a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3a_1.pdf" name="3a_1"><img src="../../../pdficon.gif"></a>
<b>A-3A.1 A New System Partitioning Method under Performance and Physical
Constraints for Multi-Chip Modules
</a><br></b>
<i>Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi (Hiroshima Univ., Japan),
Noriyoshi Yoshida (Hiroshima City Univ., Japan)</i><p>
<a href="aspabs.htm#3a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3a_2.pdf" name="3a_2"><img src="../../../pdficon.gif"></a>
<b>A-3A.2 A Robust Min-Cut Improvement Algorithm Based on Dynamic Look-Ahead
Weighting
</a><br></b>
<i>Katsunori Tani (NEC, Japan)</i><p>
<a href="aspabs.htm#3a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3a_3.pdf" name="3a_3"><img src="../../../pdficon.gif"></a>
<b>A-3A.3 Timing Influenced General-Cell Genetic Floorplanner
</a><br></b>
<i>Sadiq M. Sait, Habib Youssef, Shahid K. Tanvir, and Muhammad S. T. Benten
(King Fahd Univ. of Petroleum and Minerals, Saudi Arabia)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess3B" name="sess3B">
Session [A-3B]
Embedded System Design
</a></h3>
<i>Chair: Akihiko Yamada (Tokyo Metropolitan Univ., Japan)</i><br>
<i>Co-Chair: Jun Sato (Tsuruoka National College of Technology, Japan)</i><p>
<a href="aspabs.htm#3b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3b_1.pdf" name="3b_1"><img src="../../../pdficon.gif"></a>
<b>A-3B.1 Power Analysis of a 32-bit Embedded Microcontroller
</a><br></b>
<i>Vivek Tiwari (Princeton Univ., USA),
Mike Tien-Chien Lee (Fujitsu Labs. of America, USA)</i><p>
<a href="aspabs.htm#3b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3b_2.pdf" name="3b_2"><img src="../../../pdficon.gif"></a>
<b>A-3B.2 Assessing the Feasibility of Interface Designs before their Implementation
</a><br></b>
<i>Marco A. Escalante, Nikitas J. Dimopoulos (Univ. of Victoria, Canada)</i><p>
<a href="aspabs.htm#3b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3b_3.pdf" name="3b_3"><img src="../../../pdficon.gif"></a>
<b>A-3B.3 A Hardware-Software Co-simulator for Embedded System Design and Debugging
</a><br></b>
<i>A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie,
D. Tarrodaychik,
O. Yamamoto (Mitsubishi Electric Research Laboratories, Inc., USA)</i><p>
<hr>
<h3>
Session [A-3C] <a href="aspabs.htm#sess3C" name="sess3C">
<SPECIAL SESSION> System-Level Design Automation Activities in Korea (2)
</a></h3>
<i>Chair: Chong-Min Kyung, KAIST, Korea</i><p>
<a href="aspabs.htm#3c_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3c_1.pdf" name="3c_1"><img src="../../../pdficon.gif"></a>
<b>A-3C.1 Integrated Interconnect Circuit Modeling for VLSI Design
</a><br></b>
<i>Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim
(LG Semiconductor Inc., Korea)</i><p>
<a href="aspabs.htm#3c_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3c_2.pdf" name="3c_2"><img src="../../../pdficon.gif"></a>
<b>A-3C.2 Architectural Simulation for a Programmable DSP Chip Set
</a><br></b>
<i>Jong Tae Lee, Jaemin Kim, and Jae Cheol Son
(Samsung Electronics Co., Ltd., Korea)</i><p>
<a href="aspabs.htm#3c_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3c_3scn.pdf" name="3c_3"><img src="../../../pdficon.gif"></a>
<b>A-3C.3 System-Level Verification of CDMA Modem ASIC
</a><br></b>
<i>GyeongLyong Park, KyungHi Chang, Jaeseok Kim, and Kyungsoo Kim
(ETRI, Korea)</i><p>
<a href="aspabs.htm#3c_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/3c_4.pdf" name="3c_4"><img src="../../../pdficon.gif"></a>
<b>A-3C.4 A Digital Audio Signal Processor for Cellular Phone Application
</a><br></b>
<i>Jeongsik Yang, Chanhong Park, Beomsup Kim (KAIST, Korea)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess4A" name="sess4A">
Session [A-4A]
Routing
</a></h3>
<i>Chair: Jason Cong (Univ. of California, Los Angeles, USA)</i><br>
<i>Co-Chair: Takashi Mitsuhashi (Toshiba Corp., Japan)</i><p>
<a href="aspabs.htm#4a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4a_1.pdf" name="4a_1"><img src="../../../pdficon.gif"></a>
<b>A-4A.1 Region Definition and Ordering Assignment with the Minimization of
the Number of Switchboxes
</a><br></b>
<i>Jin-Tai Yan (National Chiao Tung Univ., Taiwan)</i><p>
<a href="aspabs.htm#4a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4a_2.pdf" name="4a_2"><img src="../../../pdficon.gif"></a>
<b>A-4A.2 A Three-Layer Over-the-Cell Multi-Channel Routing Method for a New
Cell Model
</a><br></b>
<i>Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi (Hiroshima Univ., Japan),
Noriyoshi Yoshida (Hiroshima City Univ., Japan)</i><p>
<a href="aspabs.htm#4a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4a_3.pdf" name="4a_3"><img src="../../../pdficon.gif"></a>
<b>A-4A.3 Pin Assignment and Routing on a Single-Layer Pin Grid Array
</a><br></b>
<i>Man-Fai Yu, Wayne Wei-Ming Dai (Univ. of California, Santa Cruz, USA)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess4B" name="sess4B">
Session [A-4B]
Design for Testability
</a></h3>
<i>Chair: Yervant Zorian (AT&T, USA)</i><br>
<i>Co-Chair: Kiyoshi Furuya (Chuo Univ., Japan)</i><p>
<a href="aspabs.htm#4b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4b_1.pdf" name="4b_1"><img src="../../../pdficon.gif"></a>
<b>A-4B.1 Design for Testability Using Register-Transfer Level Partial Scan
Selection
</a><br></b>
<i>Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta,
Yuji Takai, Michihiro Matsumoto,
Michiaki Muraoka (Matsushita Electric Industrial Co., Ltd., Japan)</i><p>
<a href="aspabs.htm#4b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4b_2.pdf" name="4b_2"><img src="../../../pdficon.gif"></a>
<b>A-4B.2 A Built-In Self Test Scheme for VLSI
</a><br></b>
<i>T. Raju Damarla (GEO Centers, Inc, USA),
Wei Su, Gerald T. Michael (US Army Research Labs, USA),
Moon J. Chung (Michigan State Univ., USA),
Charles E. Stroud (Univ. of Kentucky, USA)</i><p>
<a href="aspabs.htm#4b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4b_3.pdf" name="4b_3"><img src="../../../pdficon.gif"></a>
<b>A-4B.3 BIST with Negligible Aliasing through Random Cover Circuits
</a><br></b>
<i>T. Bogue, H. Jürgensen (Univ. of Western Ontario, Canada),
M. Gössel (Univ. of Potsdam, Germany)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess4C" name="sess4C">
Session [A-4C]
Logic Synthesis of Sequential Circuits
</a></h3>
<i>Chair: Sunil D. Sherlekar (Indian Inst. of Technology, India)</i><br>
<i>Co-Chair: Ryuichi Takahashi (Hiroshima City Univ., Japan)</i><p>
<a href="aspabs.htm#4c_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4c_1.pdf" name="4c_1"><img src="../../../pdficon.gif"></a>
<b>A-4C.1 Implicit Prime Compatible Generation for Minimizing Incompletely
Specified Finite State Machines
</a><br></b>
<i>Hiroyuki Higuchi, Yusuke Matsunaga (Fujitsu Laboratories Ltd., Japan)</i><p>
<a href="aspabs.htm#4c_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4c_2.pdf" name="4c_2"><img src="../../../pdficon.gif"></a>
<b>A-4C.2 Logic Optimization by an Improved Sequential Redundancy Addition and
Removal Technique
</a><br></b>
<i>Uwe Gläser (Schloss Birlinghoven, Germany),
Kwang-Ting Cheng (Univ. of California, Santa Barbara, USA)</i><p>
<a href="aspabs.htm#4c_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/4c_3.pdf" name="4c_3"><img src="../../../pdficon.gif"></a>
<b>A-4C.3 On Hazard-Free Implementation of Speed-Independent Circuits
</a><br></b>
<i>Alex Kondratyev, Michael Kishinevsky (Univ. of Aizu, Japan),
Alex Yakovlev (Univ. of Newcastle upon Tyne, UK)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess5A" name="sess5A">
Session [A-5A]
Technology-Driven Physical Synthesis
</a></h3>
<i>Chair: Hon-Wai Leong (National Univ. of Singapore)</i><br>
<i>Co-Chair: Shin'ichi Wakabayashi (Hiroshima Univ.)</i><p>
<a href="aspabs.htm#5a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5a_1.pdf" name="5a_1"><img src="../../../pdficon.gif"></a>
<b>A-5A.1 Extending Pitchmatching Algorithms to Layouts with Multiple Grid
Constraints
</a><br></b>
<i>Hiroshi Miyashita (NTT, Japan)</i><p>
<a href="aspabs.htm#5a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5a_2.pdf" name="5a_2"><img src="../../../pdficon.gif"></a>
<b>A-5A.2 A New Layout Synthesis for Leaf Cell Design
</a><br></b>
<i>Masahiro Fukui, Noriko Shinomiya, Toshiro Akino (Matsushita Electric Industrial Co., Ltd., Japan)</i><p>
<a href="aspabs.htm#5a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5a_3.pdf" name="5a_3"><img src="../../../pdficon.gif"></a>
<b>A-5A.3 A Layout Approach to Monolithic Microwave IC
</a><br></b>
<i>Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe (Sharp Corp., Japan),
Isao Shirakawa (Osaka Univ., Japan)</i><p>
<a href="aspabs.htm#5a_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5a_4.pdf" name="5a_4"><img src="../../../pdficon.gif"></a>
<b>A-5A.4 Performance Driven Multiple-Source Bus Synthesis Using Buffer Insertion
</a><br></b>
<i>Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Lin (Univ. of California, San Diego, USA)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess5B" name="sess5B">
Session [A-5B]
Logic Synthesis and Optimization (1)
</a></h3>
<i>Chair: Dr. Bernd Becker (Johann Wolfgang Goethe-Univ., Germany)</i><br>
<i>Co-Chair: Tetsuya Fujimoto (Sharp Corp., Japan)</i><p>
<a href="aspabs.htm#5b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5b_1.pdf" name="5b_1"><img src="../../../pdficon.gif"></a>
<b>A-5B.1 Communication Based FPGA Synthesis for Multi-Output Boolean Functions
</a><br></b>
<i>Christoph Scholl (Univ. des Saarlandes, Germany), Paul Molitor
(Martin-Luther Univ. Halle, Germany)</i><p>
<a href="aspabs.htm#5b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5b_2.pdf" name="5b_2"><img src="../../../pdficon.gif"></a>
<b>A-5B.2 Optimum PLA Folding through Boolean Satisfiability
</a><br></b>
<i>Jose M. Quintana, Maria J. Avedillo, Maria P. Parra, Jose L. Huertas
(Univ. of Sevilla, Spain)</i><p>
<a href="aspabs.htm#5b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5b_3.pdf" name="5b_3"><img src="../../../pdficon.gif"></a>
<b>A-5B.3 Technology Mapping for FPGAs with Complex Block Architectures by Fuzzy Logic Technique
</a><br></b>
<i>Jun-Yong Lee, Eugene Shragowitz (Univ. of Minnesota, USA)</i><p>
<a href="aspabs.htm#5b_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/5b_4.pdf" name="5b_4"><img src="../../../pdficon.gif"></a>
<b>A-5B.4 Logic Rectification and Synthesis for Engineering Change
</a><br></b>
<i>Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska
(Univ. of California, Santa Barbara, USA),
Kuang-Chien Chen (Fujitsu Labs. of America, Inc., USA)</i><p>
<hr>
Session [A-5C]
<PANEL> Future Direction of Synthesizability and Interoperability of HDL's: Part-1
</a></h3>
Chair: <i>Masaharu Imai (Toyohashi Univ. of Technology, Japan)</i><br>
Co-Chair: <i>Eugenio Villar (Univ. of Cantabria, Spain)</i><br>
Panelists: <i>Raul Camposano (Synopsys, USA),
Andrew Guyler (Mentor Graphics, USA),
Victor Berman (Cadence Design Systems, USA),
Jeffrey Fox (Viewlogic, USA),
Sunil D. Sherlekar (IIT Bombay, India),
Shigeaki Hakusui (Harmonix, USA)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess6A" name="sess6A">
Session [A-6A]
CAD Algorithms for FPGAs
</a></h3>
<i>Chair: Gabriele Saucier (INPG, France)</i><br>
<i>Co-Chair: Akihiro Tsutsui (NTT, Japan)</i><p>
<a href="aspabs.htm#6a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6a_1.pdf" name="6a_1"><img src="../../../pdficon.gif"></a>
<b>A-6A.1 A New K-Way Partitioning Approach for Multiple Types of FPGAs
</a><br></b>
<i>Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth
(Technical Univ. of Munich, Germany)</i><p>
<a href="aspabs.htm#6a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6a_2.pdf" name="6a_2"><img src="../../../pdficon.gif"></a>
<b>A-6A.2 Maple-opt: A Simultaneous Technology Mapping, Placement, and Global
Routing Algorithm for FPGAs with Performance Optimization
</a><br></b>
<i>Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki (Waseda Univ., Japan)</i><p>
<a href="aspabs.htm#6a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6a_3.pdf" name="6a_3"><img src="../../../pdficon.gif"></a>
<b>A-6A.3 Routing on Regular Segmented 2-D FPGAs
</a><br></b>
<i>Yu-Liang Wu (Cadence Design Systems, Inc., USA),
Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, USA)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess6B" name="sess6B">
Session [A-6B]
Logic Synthesis and Optimization (2)
</a></h3>
<i>Chair: Tsutomu Sasao (Kyshu Inst. Technology, Japan)</i><br>
<i>Co-Chair: Shin-ichi Minato (NTT, Japan)</i><p>
<a href="aspabs.htm#6b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6b_1scn.pdf" name="6b_1"><img src="../../../pdficon.gif"></a>
<b>A-6B.1 Flexible Optimization of Fixed Polarity Reed-Muller Expansions for
Multiple Output Completely and Incompletely Specified Boolean Functions
</a><br></b>
<i>Chip-Hong Chang, Bogdan J. Falkowski (Nanyang Technological Univ., Singapore)</i><p>
<a href="aspabs.htm#6b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6b_2.pdf" name="6b_2"><img src="../../../pdficon.gif"></a>
<b>A-6B.2 GRMIN: A Heuristic Simplification Algorithm for Generalized Reed-Muller Expressions
</a><br></b>
<i>Debatosh Debnath, Tsutomu Sasao (Kyushu Inst. of Technology, Japan)</i><p>
<a href="aspabs.htm#6b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6b_3.pdf" name="6b_3"><img src="../../../pdficon.gif"></a>
<b>A-6B.3S Learning Heuristics by Genetic Algorithms
</a><br></b>
<i>Rolf Drechsler, Bernd Becker (Johann Wolfgang Goethe-Univ., Germany)</i><p>
<a href="aspabs.htm#6b_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/6b_4.pdf" name="6b_4"><img src="../../../pdficon.gif"></a>
<b>A-6B.4S Optimization Methods for Lookup-Table-Based FPGAs Using Transduction Method
</a><br></b>
<i>Shigeru Yamashita, Yahiko Kambayashi (Kyoto Univ., Japan),
Saburo Muroga (Univ. of Illinois, USA)</i><p>
<hr>
<h3> <a href="../../pdffiles/6c_0.pdf" name="sess6C">
Session [A-6C]
<PANEL> Future Direction of Synthesizability and Interoperability of HDL's: Part-2
</a></h3>
<i>Chair: Eugenio Villar (Univ. of Cantabria, Spain)</i><br>
<i>Co-Chair: Masaharu Imai (Toyohashi Univ. of Technology, Japan)</i><br>
<i>Panelists: Raul Camposano (Synopsys, USA),
Andrew Guyler (Mentor Graphics, USA),
Victor Berman (Cadence Design Systems, USA),
Jeffrey Fox (Viewlogic, USA),
Sunil D. Sherlekar (IIT Bombay, India),
Shigeaki Hakusui (Harmonix, USA)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess7A" name="sess7A">
Session [A-7A]
Modeling and Simulation
</a></h3>
<i>Chair: David Skellern (Macquarie Univ., Australia)</i><br>
<i>Co-Chair: Tetsuro Kage (Fujitsu Laboratories, Japan)</i><p>
<a href="aspabs.htm#7a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7a_1.pdf" name="7a_1"><img src="../../../pdficon.gif"></a>
<b>A-7A.1 A New and Accurate Interconnection Delay Time Evaluation in a General
Tree-Type Network
</a><br></b>
<i>D. Deschacht, C. Dabrin (Univ. Montpellier II, France)</i><p>
<a href="aspabs.htm#7a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7a_2.pdf" name="7a_2"><img src="../../../pdficon.gif"></a>
<b>A-7A.2 An Efficient Logic/Circuit Mixed-Mode Simulator for Analysis of Power
Supply Voltage Fluctuation
</a><br></b>
<i>Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita (Hitachi, Ltd., Japan)</i><p>
<a href="aspabs.htm#7a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7a_3.pdf" name="7a_3"><img src="../../../pdficon.gif"></a>
<b>A-7A.3 A Model-Adaptable MOSFET Parameter Extraction System
</a><br></b>
<i>Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru (Kyoto Univ., Japan)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess7B" name="sess7B">
Session [A-7B] Extension of Binary Decision Diagrams
</a></h3>
<i>Chair: Tomoyuki Fujita (NEC, Japan)</i><br>
<i>Co-Chair: Yusuke Matsunaga (Fujitsu Laboratories, Japan)</i><p>
<a href="aspabs.htm#7b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7b_1.pdf" name="7b_1"><img src="../../../pdficon.gif"></a>
<b>A-7B.1 Improved Computational Methods and Lazy Evaluation of the Ordered
Ternary Decision Diagram
</a><br></b>
<i>Per Lindgren (Luleä Inst. of Technology, Sweden)</i><p>
<a href="aspabs.htm#7b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7b_2.pdf" name="7b_2"><img src="../../../pdficon.gif"></a>
<b>A-7B.2 Some Remarks about Spectral Transform Interpretation of MTBDDs and
EVBDDs
</a><br></b>
<i>Radomir S. Stankovic (Yugoslavia)</i><p>
<a href="aspabs.htm#7b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/7b_3.pdf" name="7b_3"><img src="../../../pdficon.gif"></a>
<b>A-7B.3 Manipulation of Regular Expressions Under Length Constraints Using
Zero-Suppressed-BDDs
</a><br></b>
<i>Shinya Ishihara, Shin-ichi Minato (NTT, Japan)</i><p>
<hr>
<h3> <a href="../../pdffiles/7c_0.pdf" name="sess7C">
Session [A-7C]
PANEL: How Sub-Micron Delay and Timing Issues Will Be Solved?
</a></h3>
Chair: <i>Hitoshi Yoshizawa(NEC, Japan)</i><br>
Panelists: <i>Ahsan Bootehsaz, Dennis B. Brophy, Donald R. Cottrell,
Antun Domic, Vassilios Gerousis, Tamotsu Hiwatashi</i><p>
<hr>
<h3> <a href="aspabs.htm#sess8A" name="sess8A">
Session [A-8A]
Placement
</a></h3>
<i>Chair: Wayne W.-M. Dai (Univ. of California at Santa Cruz, USA)</i><br>
<i>Co-Chair: Masato Edahiro (NEC, Japan)</i><p>
<a href="aspabs.htm#8a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8a_1.pdf" name="8a_1"><img src="../../../pdficon.gif"></a>
<b>A-8A.1 Exploiting Signal Flow and Logic Dependency in Standard Cell Placement
</a><br></b>
<i>Jason Cong, Dongmin Xu (Univ. of California, Los Angeles, USA)</i><p>
<a href="aspabs.htm#8a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8a_2.pdf" name="8a_2"><img src="../../../pdficon.gif"></a>
<b>A-8A.2 A New Performance Driven Placement Method with the Elmore Delay Model
for Row Based VLSIs
</a><br></b>
<i>Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi,
Yutaka Nishimaru (Hiroshima Univ., Japan),
Noriyoshi Yoshida (Hiroshima City Univ., Japan)</i><p>
<a href="aspabs.htm#8a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8a_3.pdf" name="8a_3"><img src="../../../pdficon.gif"></a>
<b>A-8A.3 A Neural Network Approach to the Placement Problem
</a><br></b>
<i>Morteza Saheb Zamani, Graham R. Hellestrand (Univ. of New South Wales, Australia)</i><p>
<a href="aspabs.htm#8a_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8a_4.pdf" name="8a_4"><img src="../../../pdficon.gif"></a>
<b>A-8A.4 Fanout-Tree Restructuring Algorithm for Post-Placement Timing Optimization
</a><br></b>
<i>T. Aoki, M. Murakata, T. Mitsuhashi, N. Goto (Toshiba Corp., Japan)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess8B" name="sess8B">
Session [A-8B]
Application Specific Design
</a></h3>
<i>Chair: Hiroaki Kunieda (Tokyo Inst. of Technology, Japan)</i><br>
<i>Co-Chair: Tatsuya Fujii (NTT, Japan)</i><p>
<a href="aspabs.htm#8b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8b_1.pdf" name="8b_1"><img src="../../../pdficon.gif"></a>
<b>A-8B.1 Synthesis and Simulation of Digital Demodulator for Infrared Data
Communication
</a><br></b>
<i>Hiroshi Uno, Toru Chiba (SHARP Corp., Japan), Keiji Kumatani,
Isao Shirakawa (Osaka Univ., Japan)</i><p>
<a href="aspabs.htm#8b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8b_2.pdf" name="8b_2"><img src="../../../pdficon.gif"></a>
<b>A-8B.2 A Design of High-Performance Multiplier for Digital Video Transmission
</a><br></b>
<i>Keisuke Okada, Shun Morikawa, Isao Shirakawa
(Osaka Univ., Japan), Sumitaka Takeuchi (Mitsubishi Electric Corp., Japan)</i><p>
<a href="aspabs.htm#8b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8b_3.pdf" name="8b_3"><img src="../../../pdficon.gif"></a>
<b>A-8B.3 Design Automation for Integrated Continuous-Time Filters
Using Integrators
</a><br></b>
<i>Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii
(Tokyo Inst. of Technology, Japan, Toshiba Corporation)</i><p>
<a href="aspabs.htm#8b_4"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8b_4.pdf" name="8b_4"><img src="../../../pdficon.gif"></a>
<b>A-8B.4S A Hardware-Oriented Design for Weighted Median Filters
</a><br></b>
<i>Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao (National Taiwan Univ., Taiwan)</i><p>
<a href="aspabs.htm#8b_5"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/8b_5.pdf" name="8b_5"><img src="../../../pdficon.gif"></a>
<b>A-8B.5S Techniques for Low Power Realization of FIR Filters
</a><br></b>
<i>Mahesh Mehendale (Texas Instruments India Ltd., India), S. D.
Sherlekar, G. Venkatesh (Silicon Automation Systems (India)Ltd.)</i><p>
<hr>
<h3> <a href="../../pdffiles/8c_0.pdf" name="sess8C">
Session [A-8C]
Invited Tutorial: EDIF Version 350/400 and Information Modelling
</a></h3>
<i>Chair: Mike Church (Zuken-Redac, UK)</i><br>
<i>Speaker: Hilary J. Kahn</i><p>
<hr>
<h3> <a href="aspabs.htm#sess9A" name="sess9A">
Session [A-9A]
Delay Abstraction/Design Verification
</a></h3>
<i>Chair: Kewal K. Saluja (Univ. of Wisconsin, USA)</i><br>
<i>Co-Chair: Kazuhiro Iwasaki (Chiba Univ., Japan)</i><p>
<a href="aspabs.htm#9a_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9a_1.pdf" name="9a_1"><img src="../../../pdficon.gif"></a>
<b>A-9A.1 Delay Abstraction in Combinational Logic Circuits
</a><br></b>
<i>Noriya Kobayashi (NEC Corp., Japan), Sharad Malik (Princeton Univ., USA)</i><p>
<a href="aspabs.htm#9a_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9a_2.pdf" name="9a_2"><img src="../../../pdficon.gif"></a>
<b>A-9A.2 Limits of Using Signatures for Permutation Independent
Boolean Comparison
</a><br></b>
<i>Janett Mohnke, Paul Molitor (Martin-Luther Univ. Halle, Germany),
Sharad Malik (Princeton Univ., USA)</i><p>
<a href="aspabs.htm#9a_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9a_3.pdf" name="9a_3"><img src="../../../pdficon.gif"></a>
<b>A-9A.3 A Tool for Measuring Quality of Test Pattern for LSIs' Functional Design
</a><br></b>
<i>Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami (NTT, Japan)</i><p>
<hr>
<h3> <a href="aspabs.htm#sess9B" name="sess9B">
Session [A-9B]
High Level Synthesis (2)
</a></h3>
<i>Chair: Youn-Long Steve Lin (Tsing Hua Univ., Taiwan)</i><br>
<i>Co-Chair: Vasily Moshnyaga (Kyoto Univ., Japan)</i><p>
<a href="aspabs.htm#9b_1"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9b_1.pdf" name="9b_1"><img src="../../../pdficon.gif"></a>
<b>A-9B.1 Search Space Reduction in High Level Synthesis by Use of an Initial Circuit
</a><br></b>
<i>Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine(Toshiba Corp., Japan)</i><p>
<a href="aspabs.htm#9b_2"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9b_2.pdf" name="9b_2"><img src="../../../pdficon.gif"></a>
<b>A-9B.2A Datapath Synthesis System for the Reconfigurable Datapath Architecture
</a><br></b>
<i>Reiner W. Hartenstein, Rainer Kress (Univ. of Kaiserslautern, Germany)</i><p>
<a href="aspabs.htm#9b_3"><img src="../../../absicon.gif"></a>
<a href="../../pdffiles/9b_3.pdf" name="9b_3"><img src="../../../pdficon.gif"></a>
<b>A-9B.3 Synthesis-for-Testability Using Transformations
</a><br></b>
<i>Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy (NEC USA, USA)</i><p>
<hr>
<a href="../../pdffiles/9c_0.pdf" name="sess9C"><img src="../../../pdficon.gif"></a>
<b>Session [A-9C]
<PANEL> Electronic Data Book: Current Status of Standard Representation and
Future Perspective
</b></a><p>
Organizer: <i>Kinya Tabuchi (Mitsubishi Electric Corp., Japan)</i><br>
Chair: <i>Kinya Tabuchi (Mitsubishi Electric Corp., Japan)</i><br>
Panelists: <i>Andy Graham (CFI, USA),
Bob Yencha (Pinnacles Group, National Semiconductor, USA),
Tom Jeffery (Pinnacles Group, Hitachi Micro Systems, USA),
Toshitaka Fukushima (ELISNET, Fujitsu, Japan),
Joe Prang (Aspect Development Inc., USA)</i><p>
</body>
</html>
]]>