13th Asia and South Pacific Design Automation Conference

ASP-DAC 2008

Date : January 21 - 24, 2008
Place: COEX, Seoul, Korea

Tutorials

Two full-day and four half-day tutorials will be presented in four parallel sessions on January 21, 2008. The tutorials are given by top experts in the fields and cover today's most important issues in system LSI design and EDA technologies: New system-level synthesis methodology, reliable chip synthesis at the system level, CAD for FPGAs, nano-meter physical design, on-chip network, and SoC verification. Continuing features of ASP-DAC2008 Tutorial

• All-in-one textbook! A textbook includes the materials for all the tutorials.
• A lunch coupon is included.

• Date: Monday, January 21, 2008 (9:00 - 17:30)
• Place: COEX, 3F
• Tutorial Chair: Taewhan Kim (Seoul Nat'l Univ., Korea)

Tutorial 1 (Full Day), Monday, January 21, 09:00 - 17:30 Room 310A

System-Level Synthesis: Functions, Architectures, and Communications

Speakers:
Alberto Sangiovanni Vincentelli (Univ. of California, Berkeley)
Jason Cong (Univ. of California, Los Angeles)
Radu Marculescu (CMU)
Clas A. Jacobson (United Technologies Research Center)

Abstract:
Each of the grand themes in the future of design of integrated systems and circuits proposes to develop solutions addressing a particular problem, such as power, concurrency, variability or reliability, and brings together aspects from multiple communities such as modeling, architecture exploration, design synthesis, verification, and test. To do this successfully requires an underlying and common design technology framework for complex heterogeneous systems, which can be shared over technology domains and optimization targets. At GSRC, we have expended considerable effort in developing the basic foundations for such a framework. Yet, while we have made major inroads, plenty of challenges remain to be resolved if we want to successfully address the challenges raised by the technology advances. More specifically, the following design needs can be identified:

• Formal specifications that include declarative and operational components expressed in continuous and discrete time domains.
• Design as a formally verified refinement process on a set of consistent abstraction layers where appropriate interfaces are built to handle heterogeneous signal domains, thereby ensuring vertical consistency.
• Optimized and automatic design space exploration with heterogeneous implementation architectures.
• Mapping of functionality onto architectures exploiting multi-processor optimized compilers, high-level hardware synthesis, and automatic communication synthesis.
• Automatic extraction of architecture models with stochastic models to capture uncertainties typical of nano-fabrics and mapping of functionalities onto these architectures with optimization of expected performance and cost.
• An integration framework based on formalized models where the design process can be adaptively defined according to the application domain and offering the opportunity to different constituencies to leverage each other's work.

This tutorial covers recent advances in system-level design and synthesis achieved in the core foundations for heterogeneous system-level design of the Giga-scale System-level Research Center (GSRC). We start with the foundations of the methodology posed as the basis for the multi-year effort of this theme that has been adopted broadly in industry: platform-based design. Following the introduction of the overall methodology, we proceed to present the development of an integration framework, Metropolis II that builds upon the work of Metropolis. This framework aims at the system design problem where software and hardware are important implementation methods but are determined by overall system consideration and specification. We describe the execution semantics as well as the modeling approach we have followed. This framework and the methodology it supports are exemplified with a few test cases taken from our industrial partners in particular, automobiles and building management. The second part of the tutorial presents recent developments in automatic system level synthesis for complex functional blocks starting from behavior-level specification such as C, C++, SystemC, or Metropolis metamodels. We will present latest results on constraint-driven scheduling from totally untimed models or partially timed models, resource binding and microarchitecture generation for area, performance, and power optimization, and simultaneous behavior and communication synthesis. We shall also present the results on synthesis of application-specific instruction-set processor (ASIPs) as an alternative solution for efficient implementation of the complex function blocks. These techniques have been integrated into the xPilot synthesis system and we shall discuss its results on several real-life examples. The third part of the tutorial addresses the emerging area of NoC design and presents several research issues where the concept of "network" is at the forefront of multi-core processing. Specifically, we plan to discuss performance models and optimization techniques that can be used to design different NoC architectures for multimedia applications, while reasoning about performance, energy, and fault-tolerance tradeoffs. To better understand the advantages in terms of area, performance, and energy consumption offered by the NoC approach, we discuss a concrete NoC-based implementation of an MPEG-2 encoder and provide direct measurements using an FPGA prototype and actual video clips. Finally, we present the practice and results of these state-of-art system-level design and synthesis techniques in an industrial setting. In particular the system level design issues that arise in incorporating networked embedded systems in infrastructure areas (building functionality, HVAC/R, power generation and distribution) are covered through several examples.

Tutorial 2 (Full Day), Monday, January 21, 09:00 - 17:30 Room 310BC

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips

Speakers:
Nikil Dutt (Organizer, Univ. of California, Irvine)
Fadi Kurdahi (Univ. of California, Irvine)
Ahmed Eltawil (Univ. of California, Irvine)
Sani Nassif (IBM)

Abstract:
Designers of next generation Systems-on-Chip (SoCs) face daunting challenges in generating high yielding architectures that integrate vast amounts of logic and memories in a minimum die size, while simultaneously minimizing power consumption. Advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. Fortunately, many important application domains (e.g., communication and multimedia) are inherently error-aware, allowing a range of designs with a specified Quality of Service (QoS) to be generated. This tutorial addresses this notion of error-awareness across multiple abstraction layers - application, architectural platform, and technology - for next generation SoCs. The intent is to allow exploration and evaluation of a large, previously invisible design space exhibiting a wide range of power, performance, and cost attributes. To achieve this one must synergistically bring together expertise at each abstraction layer: in communication/multimedia applications, SoC architectural platforms, and advanced circuits/technology, in order to allow effective co-design across these abstraction layers. Such approaches must be validated and tested in real applications. An ideal context for the convergence of such applications are handheld multimedia communication devices in which a WCDMA modem and an H.264 encoder must co-exist, potentially with other applications such as imaging. These applications present an example of a system that has a wide scope, executes in highly dynamic environment and presents interesting opportunities for tradeoff analysis and optimization.

TUTORIAL OUTLINE:

1. Technology Modeling
   The tutorial begins with the technological trends that highlight the increasing error-prone design process in advanced process technologies, and motivates the need for error-awareness.
2. Application Level Error-Aware Design
   Following that, we highlight approaches for error-aware design processes using typical application drivers. These applications include wireless communication systems, multimedia systems, and imaging systems. The concept of yield is extended beyond manufacturing yield to its broader perspective encompassing power, performance and error tradeoffs, enabling new dimensions of system tradeoffs.
3. Platform and higher level design tradeoffs
   This concept is then raised and then extended to the software/architectural domain, considering processors and memories, as well as upper protocol layers. Case studies are presented throughout the tutorial.

Tutorial 3 (Half Day), Monday, January 21, 09:00 - 12:30 Room 311A

Latest Advances and Future Opportunities on CAD for FPGAs

Speakers:
Deming Chen (Univ. of Illinois, Urbana-Champaign)
Martin D.F. Wong (Organizer, Univ. of Illinois, Urbana-Champaign)

Abstract:
As cost and complexity for ASIC designs grow in a steady and rapid pace along the technology scaling, FPGA designs offer an attractive alternative. According to research firm Gartner/Dataquest, the year 2007 will see nearly 89,000 FPGA design starts, and will swell to 112,000 in 2010 - some 25 times that of ASICs. As major FPGA vendors pushed out their high-end 65nm platform FPGA chips, new concerns and challenges emerge for the FPGA CAD community. Although CAD for high performance is still an active research area, power and variation-aware synthesis and physical design are increasingly more important and catching people's attention. How much margin is there for optimizing performance and power through new CAD algorithms and techniques that focus on new aspects such as glitch power, multi-clock, and process variation How can ESL design methodology play a role for FPGA design space exploration What can we learn from research thrusts such as FPGA floorplan and BDD synthesis What will be the future challenges and opportunities for FPGA CAD research In this half-day tutorial, we will introduce the latest advances on CAD for FPGAs and offer our insights on these intriguing and exciting questions.

Tutorial 4 (Half Day), Monday, January 21, 09:00 - 12:30 Room 311BC

Improvements in 65/45nm Physical Implementation Flow and Methodology

Organizer and Presenter:
Andrew B. Kahng (Univ. of California, San Diego)

Abstract:
This tutorial will discuss new challenges that face developers and users of 65nm and 45nm physical implementation flows, as well as opportunities for improved design turnaround time and quality of result obtained with such flows. The tutorial is targeted to practitioners (CAD integrators, CAD R&D, physical design methodologists, back-end chip implementation groups) as well as students and researchers. Topics covered will include:

1. Introduction
   
   • Technology and library development (design rules, SPICE models, guardbands and process maturation).
   • Trajectory of layout styles (e.g., restricted layout rules vs. double-patterning) and optimization knobs (e.g., multi-Vt vs. adaptive biasing) at 45nm and below.
   • Guardbanding. Various sources of guardbanding and their costs with respect to turnaround time and design quality.
2. New variability-aware analyses
   
   • How systematic and random litho, etch, CMP non-idealities will be incorporated into golden characterization and analysis flows
   • Stress-induced variability: modeling at circuit and library levels of abstraction (STI width, dual stress liner, etc.)
   • Thermal and supply-voltage fluctuation
3. New variability-aware optimizations
   
   • How manufacturing variability can or should be captured in design flows
     • Virtual manufacturing flows
     • Statistical optimization flows
     • Correct by construction and construct by correction flows
   • Stress mitigations using placement and active-layer fill
   • Sensitivity optimizations and 'self-compensating' robust design techniques
4. New physical design challenges (and magnitude of significance)
   • Library richness and complexities (data management, synthesis/optimization failures, etc.)
   • Double-patterning lithography
   • Interconnect reliability
   • Emerging variation sources beyond-die (reticle- and wafer-scale) and within-die (dopant fluctuations, overlay, line-edge roughness, etc.)
5. Differentiating physical design techniques.
   
   • New methodologies for handle the challenges
   • "Glue" optimizations: clock and power distribution
   • Convergence: detailed placement, detailed routing and circuit optimization
   • Direct improvement of yield and reliability

Tutorial 5 (Half Day), Monday, January 21, 14:00 - 17:30 Room 311A

On-Chip Network: State-of-the-Art Industrial Solution and Academic Research

Speakers:
David Gwilt (ARM Ltd.)
Axel Jantsch (Royal Inst. of Technology)

Abstract:
On-chip bus has a significant impact on the area, power, performance and design cycle of complex SoCs. The conventional on-chip bus was based on shared buses and their hierarchical compositions. However, the ever increasing requirements of high frequency, low power, and fast design cycle require innovation in on-chip bus designs for SoCs. From industrial viewpoint, the innovation seems to apply crossbar (often called bus matrix)-based bus design. Most of academic research tackles more ambitious goals, designing 'network' on a chip. This tutorial covers recent advances of both industrial solution and academic research towards on-chip network design. In the first part of this tutorial, the presenter, Mr. David Gwilt, who is the engineering director of ARM's System Design Division, provides a tour (sub-title: "AMBA3 technology in the design of on-chip communication and data management infrastructure") through the on-chip bus design issues commonly faced by today's industry leaders in pursuit of high performance, low power and fast time-to-market. State-of-the-art commercial solutions based on crossbar components are then presented, delivering benefits that not only address all the common concerns but many of the less common ones too. The second part of this tutorial, presented by Prof. Axel Jantsch, will systematically discuss (1) the main elements in a Network on Chip (NoC), i.e. the network interface, the switch and the link, and (2) the main issues in communication networks: topology, routing, switching, flow control and offered communication services. The significance and effect of a two dimensional VLSI implementation will be emphasized throughout the tutorial. A strong emphasis is put on performance, performance models and implications of design decisions on network performance. In addition to average performance, worst case performance and quality of service will be discussed. A particular approach to analyze worst case performance will be introduced which is based on Network Calculus.

Tutorial 6 (Half Day), Monday, January 21, 14:00 - 17:30 Room 311BC

State of the Art SoC Verification Technology: Specman Based CDV, eRM, and SVM
(The Road to Better Verification is Paved with Many Acronyms)

Speakers:
Avi Behar (Cadence Design Systems, Japan)
Richard F. Rader Jr. (Samsung Electronics, Korea)

Abstract:
As complexity in the digital world continues to grow, the verification problem is growing at an even higher exponential rate. The design side of the problem has long benefited from the now classic practices of standardization and design reuse. In order to keep pace with the growing design complexity, these same concepts of standardization and reuse must be applied to the verification. We will demonstrate how methodical, reusable strategies for the creation of verification environments can come to the aid of the verification engineers and provide them the necessary techniques to support the overall design development cycle.

The opening section of the tutorial will highlight how two key methodologies enhance the productivity of verification engineers, followed by an introduction to the Cadence verification IP that implements them.

(1) Coverage Driven Verification (CDV): In a world where devices become more and more complex, the shift to CDV holds the key to moving from manual-intensive test writing to auto generation of constrained-random stimuli.

(2) System Verification Methodology (SVM): As verification takes the lion's share of the design cycle, there is much to be gained by reusing verification IP between projects as well as from to block to system to chip verification environments. SVM, a super set of the e-Reuse Methodology (eRM), presents users with the best known practices for verification reuse.

(3) Cadence's e-Verification Components (eVC): eVCs are verification IP components which embody the CDV, eRM, and SVM methodologies. Focusing on the prepackaged, reusable interface eVCs for the AXI and AHB protocol, we will demonstrate these how packages allow the verification engineer to rapidly create meaningful, complex verification environments.

The second section of the tutorial will focus on how the basic Cadence methodologies have been extended by Samsung to create an extensive, real world verification environment. This will showcase how the flexibility in the Cadence methodologies allowed customizations to create a tightly-coupled, robust methodology providing a concrete, reusable verification environment. It will emphasize how further standardization beyond the basic SVM guidelines led to a regular, well-defined solution which ultimately developed into an automated environment builder. The tutorial will wrap up with a demonstration of how these concepts grew into a GUI based verification builder for AXI/AHB/APB subsystems.