| Title | Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory Using Gate-Block Selection Algorithm |
| Author | *Jui-Yuan Hsieh, Shanq-Jang Ruan (Nat'l Taiwan Univ. of Science and Tech., Taiwan) |
| Page | pp. 316 - 321 |
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| Title | Block Cache for Embedded Systems |
| Author | *Dominic Hillenbrand, Jörg Henkel (Univ. of Karlsruhe (TH), Germany) |
| Page | pp. 322 - 327 |
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| Title | A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures |
| Author | *Aviral Shrivastava (Arizona State Univ., United States), Ilya Issenin, Nikil Dutt (Univ. of California, Irvine, United States) |
| Page | pp. 328 - 333 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Fast, Quasi-Optimal, and Pipelined Instruction-Set Extensions |
| Author | *Ajay K. Verma, Philip Brisk, Paolo Ienne (EPFL, Switzerland) |
| Page | pp. 334 - 339 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Load Scheduling: Reducing Pressure on Distributed Register Files for Free |
| Author | *Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang (Nat'l Univ. of Defense Tech., China) |
| Page | pp. 340 - 345 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |