| Title | Symmetry-Aware Placement with Transitive Closure Graphs for Analog Layout Design |
| Author | *Lihong Zhang (Memorial University of Newfoundland, Canada), C.-J. Richard Shi (University of Washington, United States), Yingtao Jiang (University of Nevada, United States) |
| Page | pp. 180 - 185 |
| Keyword | Analog integrated circuits, layout, symmetry, placement, transitive closure graph |
| Abstract | A new scheme is proposed to use transitive closure graph (TCG) to explore the full symmetry solution space in analog layout design. We define a set of TCG symmetric-feasible conditions and show that it is extremely useful in reducing the solution space. A method is presented for generating random symmetric-feasible TCGs in O(n) time preserving the TCG closure property. Experimental results have confirmed the effectiveness of the proposed symmetry-aware TCG placement algorithm. |
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| Title | Constraint-Free Analog Placement with Topological Symmetry Structure |
| Author | *Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan) |
| Page | pp. 186 - 191 |
| Keyword | placement, analog layout, symmetry, regularity, sequence-pair |
| Abstract | In analog circuits, blocks need to be
placed symmetrically to satisfying the devices matching. Different
from the existing constraint-driven approaches, the proposed
topological symmetry structure enables us to generate a symmetrical
placement without any constraint. Simulated annealing is utilized as
the framework of the optimization, and we propose new move operation
to keep the placement's topological symmetry. By inserting dummy
blocks, we present a physical skewed symmetry structure allowing
non-symmetry partly, so that to enhance the placement on area and
wire length. Besides, we incorporate regularity into the evaluation
of placement. Experiments showed that our approach generated
topological complete symmetry placements without much compromise on
chip area and wire length, compared to the placements with no
symmetry. |
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| Title | TCG-Based Muli-Bend Bus Driven Floorplanning |
| Author | Tilen Ma, *Evangeline F. Y. Young (The Chinese Univ. of Hong Kong, Hong Kong) |
| Page | pp. 192 - 197 |
| Keyword | Floorplanning, Algorithm, Bus Planning |
| Abstract | In this paper, the problem of bus driven floorplanning is addressed. Given a set of modules and bus specifications, a floorplan solution including the bus routes will be generated with the floorplan area and total bus area minimized. Some previous works have addressed this problem with restricted bus shapes of 0-bend, 1-bend or 2-bend [1]. However, in this paper, we address this bus driven floorplanning without any limitations on the shapes of the buses.
We solve this problem by a simulated annealing based floorplanner using the Transitive Closure Graph (TCG) representation. Experimental results show that we can improve over [1] significantly in terms of both run time and quality, since there are more flexibilities in routing the buses and complex shape validataion steps are not needed. For data sets with buses connecting a large number of blocks, our approach can still generate high quality solutions effectively, while the approach in [1] of restricting to 2-bend buses often cannot give any feasible solutions. |
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| Title | Large-Scale Fixed-Outline Floorplanning Design Using Convex Optimization Techniques |
| Author | *Chaomin Luo, Miguel F. Anjos (Univ. of Waterloo, Canada), Anthony Vannelli (Univ. of Guelph, Canada) |
| Page | pp. 198 - 203 |
| Keyword | fixed-outline floorplanning, convex optimization, second-order cone programming, relative position matrix , wirelength minimization |
| Abstract | Abstract — A two-stage optimization methodology is proposed
to solve the fixed-outline floorplanning problem that is a global optimization problem for wirelength minimization. In the first stage,
an attractor-repeller convex optimization model provides the relative
positions of the modules on the floorplan. The second stage
places and sizes the modules using second-order cone optimization.
A Voronoi diagram is employed to obtain a planar graph and
thus a relative position matrix to connect the two stages. Overlapfree and deadspace-free floorplans are achieved in a fixed outline and floorplans with any specified percentage of whitespace can be produced. Experimental results on GSRC benchmarks demonstrate
that we obtain significant improvements on the best results
known in the literature for these benchmarks. Most importantly,
our methodology provides greater improvement over other floorplanners
as the number of modules increases. |
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| Title | LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs |
| Author | *Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong (Tsinghua Univ., China), Jason Cong (Univ. of California, Los Angeles, United States) |
| Page | pp. 209 - 212 |
| Keyword | 3D ICs, performance, thermal via, floorplanning |
| Abstract | Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal resistances between device layers. However, it is usually difficult to get enough space at target regions to insert thermal vias. In this paper, we propose a novel analytical algorithm to re-allocate white space for 3D ICs to facilitate via insertion. Experimental results show that after reallocating whitespaces, thermal vias and total wirelength could be reduced by 14% and by 2%, respectively. It also shows that whitespace distribution with via planning alone will degrade performance by 9% while performance-aware via planning method can reduce thermal via number by 60% and the performance is kept nearly unchanged. |
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