| Title | Flow Time Minimization under Energy Constraints |
| Author | *Jian-Jia Chen (National Taiwan University, Taiwan), Kazuo Iwama (Kyoto University, Japan), Tei-Wei Kuo, Hseuh-I Lu (National Taiwan University, Taiwan) |
| Page | pp. 866 - 871 |
| Keyword | Energy-aware systems, Scheduling, Flow time minimization, Dynamic voltage scaling |
| Abstract | Power-aware and energy-efficient designs play important roles for modern hardware and software designs, especially for embedded systems. This paper targets a scheduling problem on a processor with the capability of dynamic voltage scaling (DVS), which could reduce the power consumption by slowing down the processor speed. The objective of the targeting problem is to minimize the average flow time of a set of jobs under a given energy constraint, where the flow time of a job is defined as the interval length between the arrival and the completion of the job. We consider two types of processors, which have a continuous spectrum of the available speeds or have only a finite number of discrete speeds. Two algorithms are given: (1) An algorithm is proposed to derive optimal solutions for processors with a continuous spectrum of the available speeds. (2) A greedy algorithm is designed for the derivation of optimal solutions for processors with a finite number of discrete speeds. The proposed algorithms are extended to cope with jobs with different weights for the minimization of the average weighted flow time. The proposed algorithms are also evaluated with comparisons to schedules which execute jobs at a common effective speed. |
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| Title | Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost |
| Author | Bita Gorjiara, Nader Bagherzadeh, *Pai Chou (University of California, Irvine, United States) |
| Page | pp. 872 - 877 |
| Keyword | Dynamic Power Management, real-time systems, distributed systems |
| Abstract | The development cost of low-power embedded systems can be reduced by reusing legacy designs and applying proper modifications to meet power constraints. The power management techniques for implementing distributed power managers in multi-processor systems, are very costly in terms of hardware/software modifications. In this paper, we propose a new centralized power management technique that reduces the power consumption of distributed systems at very low implementation cost. Our power manager uses the model of the system/application to compute the schedule of turn on/off commands. We applied our power management technique to a distributed software-defined radio system and achieved 60% to 87% energy savings. |
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| Title | A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation |
| Author | *Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura (Kyushu University, Japan) |
| Page | pp. 878 - 883 |
| Keyword | Process variation, Leakage power, Software-based Technique, Yield, Embedded Systems |
| Abstract | Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may even change position with changes in the operating voltage and temperature, and hence, redundancy at circuit-level is not sufficient to tolerate such threats to yield. We show that in SRAM cells this leakage depends on the cell value and propose a first software-based runtime technique that suppresses such abnormal leakages by storing safe values in the
corresponding cache lines before going to standby mode. Analysis shows the performance penalty is, in the worst case, linearly dependent to the number of so-cured cache lines while the energy saving linearly increases by the time spent in standby mode. Analysis and experimental results on commercial processors confirm that the technique is viable if the standby duration is more than a small fraction of a second. |
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