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The 12th Asia and South Pacific Design Automation Conference

Session 8C Advances in Test and Diagnosis
Time: 13:30 - 15:35 Friday, January 26, 2007
Location: Room 414+415
Chairs: Erik Larsson (Royal Inst. of Tech., Sweden), Xiaoging Wen (Kyushu Inst. of Tech., Japan)

8C-1 (Time: 13:30 - 13:55)
TitleA Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Author*Seongmoon Wang, Wenlong Wei (NEC, United States)
Pagepp. 810 - 816
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8C-2 (Time: 13:55 - 14:20)
TitleWarning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
AuthorZhuo Zhang, *Sudhakar Reddy (Univ. of Iowa, United States), Irith Pomeranz (Purdue Univ., United States)
Pagepp. 817 - 822
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8C-3 (Time: 14:20 - 14:45)
TitleA Wafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs
AuthorSudarshan Bahukudumbi, Sule Ozev, *Krishnendu Chakrabarty (Duke Univ., United States), Vikram Iyengar (IBM, United States)
Pagepp. 823 - 828
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8C-4 (Time: 14:45 - 15:10)
TitleFault Dictionary Size Reduction for Million-Gate Large Circuits
Author*Yu-Ru Hong, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 829 - 834
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8C-5 (Time: 15:10 - 15:35)
TitleCyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
Author*Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li (National Taiwan Univ., Taiwan)
Pagepp. 835 - 840
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