| Title | An Efficient Computation of Statistically Critical Sequential Paths Under Retiming |
| Author | Mongkol Ekpanyapong (Intel Corporation, United States), Xin Zhao, *Sung Kyu Lim (Georgia Institute of Technology, United States) |
| Page | pp. 547 - 552 |
| Keyword | statistical timing analysis, retiming |
| Abstract | In this paper we present the Statistical Retiming-based Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing graph and identify the statistically critical paths under retiming, which are the paths with a high probability of becoming timing-critical after retiming. SRTA enables the designers to perform circuit optimization on these paths to reduce the probability of them becoming timing bottleneck if the circuit is retimed as a post-process. We provide a comparison among static timing analysis (= STA), statistical timing analysis (= SSTA), retiming-based timing analysis (= RTA), and our statistical retiming-based timing analysis (SRTA). Our results show that the placement optimization based on SRTA achieves the best performance results. |
| PDF file |
| Title | Fast Electrical Correction Using Resizing and Buffering |
| Author | Shrirang Karandikar, *Charles J Alpert (IBM Austin Research Laboratory, United States), Mehmet Yildiz, Paul Villarrubia, Steve Quay, Tuhin Mahmud (IBM EDA, United States) |
| Page | pp. 553 - 558 |
| Keyword | Electrical correction, Slew/cap violations, buffering, gate sizing |
| Abstract | Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a circuit for optimization, the circuit has to be electrically clean -- i.e., slews on each pin have to be within certain limits, a gate cannot drive more than a certain amount of capacitance, etc. Thus far, this requirement has largely been ignored in the literature. Instead, existing methods which optimize delay are used to fix electrical violations. This leads to solutions that are unnecessarily expensive, and still leave violations that remain unfixed. There is therefore a need for an area-efficient strategy that targets the electrical state of a circuit and fixes all violations quickly. This paper explicitly defines ``electrical violations'' and presents a flexible approach (called EVE, the Electrical Violation Eliminator) for fixing these. Experimental results validate our approach. |
| PDF file |
| Title | SmartSmooth: A Linear Time Convexity Preserving Smoothing Algorithm for Numerically Convex Data with Application to VLSI Design |
| Author | Sanghamitra Roy (University of Wisconsin-Madison, United States), *Charlie Chung-Ping Chen (National Taiwan University, Taiwan) |
| Page | pp. 559 - 564 |
| Keyword | Convex optimization, Smoothing, Numerically convex, Gate sizing |
| Abstract | Convex optimization problems are very popular in the VLSI
design society due to their guaranteed convergence to a global
optimal point. While optimizing tabular data, significant fitting
efforts are required to fit the data into convex form. Fitting the
tables into analytically convex forms like posynomials, suffers from
excessive fitting errors, as the fitting problem may be non-convex.
In recent literature optimal numerically convex tables have been
proposed. Since these tables are numerical, it is extremely
important to make the table data smooth, and yet preserve its
convexity. The smoothness ensures that the convex optimizer behaves
predictably and converges quickly to the global optimal point. The
existing smoothing techniques either cannot preserve convexity, or
require very high execution time. In this paper, we propose a linear
time algorithm to smoothen a given numerically convex data
and at the same time preserve convexity. Our proposed algorithm SmartSmooth can smoothen the data in linear time without introducing any additional error on the numerically convex data. This algorithm can be a significant contribution in the field of optimization of
non-analytical data. We present our SmartSmooth results on
industrial cell libraries. SmartSmooth when applied on convex
tables produced by ConvexFit shows a 30X reduction in fitting
error over a posynomial fitting algorithm and 3X reduction in
fitting error over ConvexSmooth algorithm. |
| PDF file |
| Title | Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies |
| Author | *Zhangcai Huang, Hong Yu (The Graduate School of Information, Production and Systems, Waseda University, Japan), Atsushi Kurokawa (Sanyo Semiconductor Company, Japan), Yasuaki Inoue (The Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 565 - 570 |
| Keyword | CMOS inverter, overshooting time, nanometer technologies, timing analysis |
| Abstract | With the scaling of CMOS technology, the overshooting
time due to the input-to-output coupling capacitance
has much more significant effect on inverter delay. Moreover, the
overshooting time is also an important parameter in the short
circuit power estimation. Therefore, in this paper an effective
analytical model is proposed to estimate the overshooting time
for the CMOS inverter in nanometer technologies. Furthermore,
the influence of the process variation on the overshooting time
is illustrated based on the proposed model. And the accuracy
of the proposed model is proved to greatly agree with SPICE
simulation results. |
| PDF file |