| Title | A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects |
| Author | Ying Zhou (Texas A&M University, United States), Zhuo Li (Pextra Corp., United States), Yuxin Tian, *Weiping Shi (Texas A&M University, United States), Frank Liu (IBM Austin Research Laboratory, United States) |
| Page | pp. 450 - 455 |
| Keyword | lithography simulation, Parasitic Extraction, DFM |
| Abstract | Even with the wide adaptation of resolution enhancement techniques
in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing Layout Parasitic Extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis.
Our simulation shows that the RC parasitics
extracted from perfect GDS-II geometry can be as much as 20\% different from those extracted from the post litho/etching simulation geometry.
This paper presents a new LPE methodology and related fast algorithms
for interconnect parasitic extraction under photo-lithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient. |
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| Title | Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion |
| Author | *Youngmin Kim (University of Michigan of Ann Arbor, United States), Dusan Petranovic (Mentor Graphics , United States), Dennis Sylvester (University of Michigan of Ann Arbor, United States) |
| Page | pp. 456 - 461 |
| Keyword | metal fills, dummy, capacitance, interconnect, modeling |
| Abstract | Inserting metal fill to improve inter-level dielectric thickness planarity is an essential part of the modern design process. However, the inserted fill shapes impact the performance of signal interconnect by increasing capacitance. In this paper, we analyze and model the impact of the metal dummy on the signal capacitance with various parameters including their electrical characteristic, signal dimensions, and dummy shape and dimensions. Fill has differing impact on interconnects depending on whether the signal of interest is in the same layer as the fill or not. In particular intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has more impact on the ground capacitance component. Based on an analysis of fill impact on capacitance, we propose simple capacitance increment models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider the realistic case with both signals and metal fill in adjacent layers, we apply a weighting function approach in the ground capacitance model. We verify this model using simple test patterns and benchmark circuits and find that the models match well with field solver results (1.3% average error with much faster runtime than commercial extraction tools, the runtime overhead reduced by ~75% for all benchmark circuits). |
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| Title | Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method |
| Author | Alexandar Mitev, Michael Marefact, Dongsheng Ma, *Janet Wang (University of Arizona at Tucson, United States) |
| Page | pp. 468 - 473 |
| Keyword | performance oriented , parameter reduction |
| Abstract | With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing
interface becomes more and more complicated. The resultant
process variability causes a number of issues in the new generation IC design.
One of the biggest challenges is the enormous number of process variation related parameters.
These parameters represent numerous local and global variations,
and pose a heavy burden in today's chip verification and design.
This paper proposes a new way of reducing the statistical variations
(which include both process parameters and design variables) according to
their impacts on the overall circuit performance. The new approach creates an
effective reduction subspace (ERS) and provides a transformation matrix by using
the mean and variance of the response surface. With the generated transformation matrix,
the proposed method maps the original statistical variations to a smaller set of variables
with which we process variability analysis. Thus, the computational cost due to the
number of variations is greatly reduced. Experimental results show that by using new method
we can achieve 20% to 50% parameter reduction with only less than 5% error on average. |
| PDF file |
| Title | Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations |
| Author | *Jun Tao, Xuan Zeng (Fudan University, China), Wei Cai (University of North Carolina at Charlotte, United States), Yangfeng Su (Fudan University, China), Dian Zhou (University of Texas at Dallas, United States), Charles Chiang (Synopsys Inc., United States) |
| Page | pp. 474 - 479 |
| Keyword | process variation, steady-state analysis, Stochastic Collocation Algorithm, Sparse Grid Technique |
| Abstract | Abstract—In this paper, Stochastic Collocation Algorithm
combined with Sparse Grid technique (SSCA) is proposed to
deal with the periodic steady-state analysis for nonlinear systems
with process variations. Compared to the existing approaches,
SSCA has several considerable merits. Firstly, compared
with the moment-matching parameterized model order reduction
(PMOR) which equally treats the circuit response on
process variables and frequency parameter by Taylor approximation,
SSCA employs Homogeneous Chaos to capture the impact of
process variations with exponential convergence rate and adopts
Fourier series or Wavelet Bases to model the steady-state behavior
in time domain. Secondly, contrary to Stochastic Galerkin
Algorithm (SGA), which is efficient for stochastic linear system
analysis, the complexity of SSCA is much smaller than that of
SGA for nonlinear case. Thirdly, different from Efficient Collocation
Method, the heuristic approach which may results in “Rank
deficient problem” and “Runge phenomenon”, Sparse Grid technique
is developed to select the collocation points needed in SSCA
in order to reduce the complexity while guaranteing the approximation
accuracy. Furthermore, though SSCA is proposed for
the stochastic nonlinear steady-state analysis, it can be applied
for any other kinds of nonlinear system simulation with process
variations, such as transient analysis, etc.. |
| PDF file |