| Title | Abstract, Multifaceted Modeling of Embedded Processors for System Level Design |
| Author | *Gunar Schirner, Andreas Gerstlauer, Rainer Doemer (University of California, Irvine, United States) |
| Page | pp. 384 - 389 |
| Keyword | abstract processor modeling, abstract computation, embedded software, system level design |
| Abstract | Embedded software is playing an increasing role in todays SoC designs.
It allows a flexible adaptation to evolving standards and to
customer specific demands. As software emerges more and more as a
design bottleneck, early, fast, and accurate simulation of
software becomes crucial. Therefore, an efficient modeling of
programmable processors at high levels of abstraction is required.
In this article, we focus on abstraction of computation
and describe our abstract modeling of embedded processors.
We combine the computation modeling with task scheduling
support and accurate interrupt handling into a versatile, multi-faceted processor model with varying levels of features.
Incorporating the abstract processor model into a communication model, we achieve fast co-simulation of a complete custom target architecture
for a system level design exploration.
We demonstrate the effectiveness of our approach using
an industrial strength telecommunication example executing on a Motorola DSP architecture. Our results indicate the tremendous value of abstract processor modeling. Different feature levels achieve a simulation speedup of up to 6600 times with an error of less than 8% over a ISS based simulation. On the other hand, our full featured model exhibits a 3% error in simulated timing with a 1800 times speedup. |
| PDF file |
| Title | Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC |
| Author | *Patrice Gerin, Hao Shen, Alexandre Chureau, Aimen Bouchhima, Ahmed Amine Jerraya (TIMA Laboratory, France) |
| Page | pp. 390 - 395 |
| Keyword | HW/SW Interface, Service-based model, MPSoC, Transaction Accurate |
| Abstract | At high abstraction level, Multi-Processor System-On-Chip (SoC) designs are specified as assembling of IPs which can be Hardware or Software. The refinement of communication between these different IPs, known as hardware/software interfaces, is widely seen as the design bottlneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels.
In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the Transaction Accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation. |
| PDF file |
| Title | A Retargetable Software Timing Analyzer Using Architecture Description Language |
| Author | *Xianfeng Li (Peking University, China), Abhik Roychoudhury, Tulika Mitra (National Univeristy of Singapore, Singapore), Prabhat Mishra (University of Florida, United States), Xu Cheng (Peking University, China) |
| Page | pp. 396 - 401 |
| Keyword | Worst Case Execution Time, Retargetability, Architecture Description Language |
| Abstract | Worst Case Execution Time (WCET) is an essential input
for performance and schedulability analysis of real-time systems.
Static WCET analysis requires program path analysis and
microarchitecture modeling. Despite almost two decades of research,
WCET analysis has not enjoyed wide acceptance in industry. This is in
part due to the difficulty in microarchitecture modeling of modern
processors. Given the large number of embedded processors available
in the market, retargetability of the WCET analysis framework is a
serious issue. In this paper, we address it using Architecture
Description Language (ADL). Starting with the ADL of a target
processor, the proposed framework automatically generates graph-based
execution models to capture timing effects of instructions in the
pipeline. This pipeline model coupled with parameterized models of
cache and branch prediction lead to a WCET framework that is safe,
accurate and retargetable. |
| PDF file |